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Circuit for generating two closely adjacent frequencies

Assignee: Siemens AG
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Filing: 1988-09-06
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Granted: 1990-02-27
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Expires: 2008-09-06
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Abstract

Abstract A circuit for generating two closely adjacent frequencies includes two oscillators each generating one of two closely adjacent frequencies. A PLL circuit is connected to the oscillators for regulating the frequencies. The PLL circuit performs a frequency comparison of the frequency generated by only one of the oscillators with a reference frequency to generate a frequency comparison output signal of the PLL circuit, and it regulates the frequencies of both of the oscillators as a function of the frequency comparison output signal of the PLL circuit.

Inventors

  • 👤 Manfred Ley

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 21:00
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03L7/099; H03L7/0995; H03B; H03B2200/00; H03B2200/0014; H03B2200/0022

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 144 words
Circuit for generating two closely adjacent frequencies, comprising two oscillators each generating one of two closely adjacent frequencies, and a PLL circuit connected to said oscillators for regulating the frequencies, said PLL circuit including means for performing a frequency comparison of the frequency generated by only one of said oscillators with a reference frequency to generate a frequency comparison output signal of said PLL circuit, and for regulating the frequencies of both of said oscillators as a function of the frequency comparison output signal of said PLL circuit; wherein said oscillators are ring oscillators formed by ECL inverters; including means for defining the frequencies of said ring oscillators formed by ECL inverters with a dissimilar value of a frequency-determining magnitude, and means for regulating the frequencies by adjusting the value of the frequency-determining magnitude through the frequency comparison output signal of the PLL circuit.
Claim 2
Dependent Claim 144 words
Circuit for generating two closely adjacent frequencies, comprising two oscillators each generating one of two closely adjacent frequencies, and a PLL circuit connected to said oscillators for regulating the frequencies, said PLL circuit including means for performing a frequency comparison of the frequency generated by only one of said oscillators with a reference frequency to generate a frequency comparison output signal of said PLL circuit, and for regulating the frequencies of both of said oscillators as a function of the frequency comparison output signal of said PLL circuit; wherein said oscillators are ring oscillators formed by ECL inverters; including means for defining the frequencies of said ring oscillators formed by ECL inverters with a dissimilar value of a frequency-determining magnitude, and means for regulating the frequencies by adjusting the value of the frequency-determining magnitude through the frequency comparison output signal of the PLL circuit.
Claim 3
Dependent Claim 48 words
Circuit according to claim 1, wherein said ring oscillators have an emitter follower with a delay capacitor forming the frequency-determining magnitude, and the regulation by the frequency comparison output signal of the PLL circuit is in the form of a regulation of the current of said emitter follower.
Claim 4
Dependent Claim 20 words
Circuit according to claim 2, wherein said ring oscillators are electrically and geometrically identical and symmetrical in an integrated circuit.

References Cited (Backward Citations)

US4097816A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-02-26 1993-08-28 1994-02-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-02-26 1997-08-28 1998-02-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-02-26 2001-08-28 2002-02-27 $7700.00 Window Closed / Lapsed

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