Phase comparator circuit

Claim 2

A phase comparator circuit for comparing a phase of a first input signal with that of a second input signal and outputting a first output signal and a second output signal in accordance with a result of the comparison, comprising: a first flip-flop circuit for receiving said first input signal and outputting said first output signal and an inverted output signal of said first output signal; a second flip-flop circuit for receiving said second input signal and outputting said second output signal and an inverted output signal of said second output signal; and a latch circuit, connected to said first and second flip-flop circuits, for receiving said output signals and said inverted output signals of said first and second flip-flop circuits and applying a reset signal to said first and second flip-flop circuits in accordance with said output signals and said inverted output signals; said first and second output signals being output by applying said reset signal to said first and second flip-flop circuits, when said first and second input signals are in-phase.

Claim 3

A phase comparator circuit as claimed in claim 1, wherein said first and second flip-flop circuits are formed by D-type flip-flop circuits respectively, and said latch circuit is formed by a first, a second, a third, and a fourth NAND gate circuits.

Claim 4

A phase comparator circuit as claimed in claim 1, wherein said comparator circuit is used in a phase-locked loop circuit.

Claim 5

A phase comparator circuit as claimed in claim 1, wherein said phase-locked loop circuit comprises a charge pump circuit, a low-pass filter, a voltage-controlled oscillator and a frequency divider circuit.

Claim 6

A phase comparator circuit for comparing a phase of a first input signal with a phase of a second input signal and outputting a first output signal and a second output signal in accordance with a result of the comparison, comprising: first D-type flip-flop means, having first and second outputs, for receiving said first input signal and for outputting said first output signal via said first output and an inverted output signal of said first output signal via said second output, and including D-terminal means for receiving a power supply voltage, clock pulse terminal means for receiving said first input signal and reset terminal means; second D-type flip-flop means, having third and fourth outputs, for receiving said second input signal and for outputting said second output signal via said third output and an inverted output signal of said second output signal via said fourth output, and including D-terminal means for receiving a power supply voltage, clock pulse terminal means for receiving said second input signal, and reset terminal means; and latch circuit means, connected to said first and second D-type flip-flop means, for receiving said output signals and said inverted output signals of said first and second D-type flip-flop means and applying a reset signal to said reset terminal means of said first and second D-type flip-flop means in accordance with said output signals and said inverted output signals, comprising: a first NAND gate circuit having an output, a first input terminal connected to receive said first output signal, and a second input terminal connected to receive said second output signal; a second NAND gate circuit having an output, a first input terminal operatively connected to the output of said first NAND gate circuit and having a second input terminal; a third NAND gate circuit having an output, a first input terminal connected to the second output of said first flip-flop means, and a second input terminal connected to the fourth output of said second D-type flip-flop means; and a fourth NAND gate circuit having an output, a first input terminal operatively connected to the output of said second NAND gate circuit, and having a second input terminal operatively connected to the output of said fourth NAND gate circuit to output said reset signal to said second input terminal of said second NAND gate circuit; said first and second output signals being output by applying said reset signal to said first and second D-type flip-flop means when said first and second input signals are in-phase.

Claim 7

A phase comparator circuit for comparing a phase of a first input signal with a phase of a second input signal and outputting a first output signal and a second output signal in accordance with a result of the comparison, comprising: first D-type flip-flop means, having first and second outputs, for receiving said first input signal and for outputting said first output signal via said first output and an inverted output signal of said first output signal via said second output, and including D-terminal means for receiving a power supply voltage, clock pulse terminal means for receiving said first input signal and reset terminal means; second D-type flip-flop means, having third and fourth outputs, for receiving said second input signal and for outputting said second output signal via said third output and an inverted output signal of said second output signal via said fourth output, and including D-terminal means for receiving a power supply voltage, clock pulse terminal means for receiving said second input signal, and reset terminal means; and latch circuit means, connected to said first and second D-type flip-flop means, for receiving said output signals and said inverted output signals of said first and second D-type flip-flop means and applying a reset signal to said reset terminal means of said first and second D-type flip-flop means in accordance with said output signals and said inverted output signals, comprising: a first NAND gate circuit having an output, a first input terminal connected to receive said first output signal, and a second input terminal connected to receive said second output signal; a second NAND gate circuit having an output, a first input terminal operatively connected to the output of said first NAND gate circuit and having a second input terminal; a third NAND gate circuit having an output, a first input terminal connected to the second output of said first flip-flop means, and a second input terminal connected to the fourth output of said second D-type flip-flop means; and a fourth NAND gate circuit having an output, a first input terminal operatively connected to the output of said second NAND gate circuit, and having a second input terminal operatively connected to the output of said fourth NAND gate circuit to output said reset signal to said second input terminal of said second NAND gate circuit; said first and second output signals being output by applying said reset signal to said first and second D-type flip-flop means when said first and second input signals are in-phase.