US4903197A
Expired / Lapsed
US
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Memory bank selection arrangement generating first bits identifying a bank of memory and second bits addressing identified bank
Assignee: HUTTON/PRC TECHNOLOGY
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Filing: 1987-02-27
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Granted: 1990-02-20
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Expires: 2007-02-27
Abstract
Abstract A memory bank selection arrangement has a memory which is made up of smaller memories each of which has a number of banks of memory. First bits of a memory address are used by an address controller for addressing a location in a selected bank of a first of the smaller memories. The address may be incremented by the controller before being used to address a second of the smaller memories, and a carry output is generated when the first bits are incremented and there is a carry from the highest order bit thereof. The memory address also includes second bits which are input to an adder which increments the number represented by the second bits responsive to the carry out from the controller to compensate for the incrementation of said first bits. The incremented or unincremented number output from the adder is used by a selector to select a bank of the smaller memories so that they can be addressed using the incremented or unincremented first bits.
Inventors
- 👤 David A. Wallace
- 👤 Richard A. Lemay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:39
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0607
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
178 words
A memory bank selection arrangement for use in a data processing system including a memory wherein an address used for addressing said memory to read or write locations therein includes first bits for identifying a bank of said memory to be selected and addressed by second bits of said address, said arrangement comprising: an address controller for processing said second bits of said address before they are used to address a location in said memory, said address controller being responsive to a predetermined bit of the second address bits to increment said second bits, said address controller generating a carry output when the incrementing of said second bits results in there being a carry from the highest order bit of said second bits, and a bank selector to which said first bits are input, said bank selector being responsive to said carry output generated by said address controller to increment the binary number represented by said first bits and said first bits, being used to select a bank in said memory to be addressed using said second bits.
Claim 2
Dependent Claim
178 words
A memory bank selection arrangement for use in a data processing system including a memory wherein an address used for addressing said memory to read or write locations therein includes first bits for identifying a bank of said memory to be selected and addressed by second bits of said address, said arrangement comprising: an address controller for processing said second bits of said address before they are used to address a location in said memory, said address controller being responsive to a predetermined bit of the second address bits to increment said second bits, said address controller generating a carry output when the incrementing of said second bits results in there being a carry from the highest order bit of said second bits, and a bank selector to which said first bits are input, said bank selector being responsive to said carry output generated by said address controller to increment the binary number represented by said first bits and said first bits, being used to select a bank in said memory to be addressed using said second bits.
Claim 3
Dependent Claim
126 words
The invention in accordance with claim 1 wherein said bank selector comprises: an adder to which said first bits are input, and said adder is responsive to said carry output from said address controller to increment the number represented by said first bits and provide another number used to indicate said selected bank of memory, and a decoder having a plurality of output leads with one lead being connected to each bank of said memory, said decoder being responsive to the first bits, the output from said adder energizing one of said output leads and thereby enable the bank of said memory t which the energized lead is connected, said selected bank of memory then being addressed by said second bits, output from said address controller.
Claim 4
Dependent Claim
83 words
The invention in accordance with claim 1 wherein said bank selector comprises a programmable logic array circuit programmed to respond to said first bits and to said carry output from said address controller to increment the binary number represented by said first bits and generate a signal onto one of a plurality of output leads with one lead being connected to each bank of said memory, said signal enabling one bank of said memory to be addressed to read or write locations therein.
Claim 5
Dependent Claim
42 words
The invention in accordance with claim 3 wherein a number of circuits vie to use said memory and further comprising a multiplexing arrangement for connecting an address from only one of said circuits at a time to said programmable array logic circuit.
Claim 6
Dependent Claim
180 words
A memory bank selection arrangement for use in a data processing system including a memory which has a number of banks, wherein first bits of a memory address are used for addressing a location in a selected bank to read or write therein and are incrementable by an address controller before being used to address a bank of said memory, wherein said address controller generates a carry output when the incrementing of said first bits result in there being a carry from the highest order bit of said first bits, and said address includes second bits for identifying a bank in said memory to be selected and then addressed by the first bits, of said address, said arrangement comprising: a bank selector to which said second bits indicating said selected bank of memory are input, said bank selector being responsive to said carry output generated by said address controller to increment the binary number represented by said second bits, and the second bits, then being used to select a bank in said memory to be addressed using said first bits.
Claim 7
Dependent Claim
180 words
A memory bank selection arrangement for use in a data processing system including a memory which has a number of banks, wherein first bits of a memory address are used for addressing a location in a selected bank to read or write therein and are incrementable by an address controller before being used to address a bank of said memory, wherein said address controller generates a carry output when the incrementing of said first bits result in there being a carry from the highest order bit of said first bits, and said address includes second bits for identifying a bank in said memory to be selected and then addressed by the first bits, of said address, said arrangement comprising: a bank selector to which said second bits indicating said selected bank of memory are input, said bank selector being responsive to said carry output generated by said address controller to increment the binary number represented by said second bits, and the second bits, then being used to select a bank in said memory to be addressed using said first bits.
Claim 8
Dependent Claim
124 words
The invention in accordance with claim 5 wherein said bank selector comprises: an adder to which said second bits are input and responsive to said carry output from said address controller to increment the number represented by said second bits and provide another number used to indicate said selected bank of said memory, and a decoder having a plurality of output leads with one output lead being connected to each bank of said memory, said decoder being responsive to the first bits, from said adder to energize one of said output leads and thereby enable the bank of said memory to which the energized lead is connected said selected bank of memory then being addressed by said second bits, output from said address controller.
Claim 9
Dependent Claim
83 words
The invention in accordance with claim 5 wherein said bank selector comprises a programmable logic array circuit programmed to respond to said first bits and to said carry output from the address controller to increment the binary number represented by said first bits and generate a signal onto one of a plurality of output leads with one lead being connected to each bank of said memory, said signal enabling one bank of said memory to be addressed to read or write locations therein.
Claim 10
Dependent Claim
42 words
The invention in accordance with claim 7 wherein a number of circuits vie to use said memory and further comprising a multiplexing arrangement for connecting the address from only one of said circuits at a time to said programmable array logic circuit.
Claim 11
Independent Claim
144 words
A method used in a data processing system for selecting a bank in a memory which has a number of banks, wherein first bits of an address used for addressing a location in a selected bank of said memory are incrementable before being used to address the memory, wherein a carry output is generated when the incrementing of said first bits results in there being a carry from the highest order bit of said first bits, and said address includes second bits for identifying a bank in said memory to be selected and then addressed by the first bits, whether incremented or not, of said address, said method comprising the steps of: incrementing said second bits when a carry output signal is generated to compensate for the incrementation of said first bits, and using said second bits, to select a bank in said memory.
Claim 12
Independent Claim
144 words
A method used in a data processing system for selecting a bank in a memory which has a number of banks, wherein first bits of an address used for addressing a location in a selected bank of said memory are incrementable before being used to address the memory, wherein a carry output is generated when the incrementing of said first bits results in there being a carry from the highest order bit of said first bits, and said address includes second bits for identifying a bank in said memory to be selected and then addressed by the first bits, whether incremented or not, of said address, said method comprising the steps of: incrementing said second bits when a carry output signal is generated to compensate for the incrementation of said first bits, and using said second bits, to select a bank in said memory.
Claim 13
Independent Claim
182 words
A method used in a data processing system for selecting a bank in a memory which has a number of banks, wherein first bits of an address are used for addressing a location in a bank and are modifiable before being used to address said memory, said second bits of said address identify a bank in said memory to be selected and then addressed using the first bits of said address, and a third bit of said address in a control bit, said method comprising the steps of: incrementing said first bits responsive to the state of said third bit in said address before said first bits are used to address said memory, generating a carry output signal when the incrementing of said first bits results in there being a carry from the highest order bit of said first bits; and incrementing said second bits when a carry output signal is generated to compensate for the incrementation of said first bits, said second bits, then being used to select a bank in said memory which is then addressed using said first bits.
Claim 14
Independent Claim
182 words
A method used in a data processing system for selecting a bank in a memory which has a number of banks, wherein first bits of an address are used for addressing a location in a bank and are modifiable before being used to address said memory, said second bits of said address identify a bank in said memory to be selected and then addressed using the first bits of said address, and a third bit of said address in a control bit, said method comprising the steps of: incrementing said first bits responsive to the state of said third bit in said address before said first bits are used to address said memory, generating a carry output signal when the incrementing of said first bits results in there being a carry from the highest order bit of said first bits; and incrementing said second bits when a carry output signal is generated to compensate for the incrementation of said first bits, said second bits, then being used to select a bank in said memory which is then addressed using said first bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-19 | 1993-08-21 | 1994-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-19 | 1997-08-21 | 1998-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-19 | 2001-08-21 | 2002-02-20 | $7700.00 | Window Closed / Lapsed |