Runaway detecting system for CPU

Claim 1

A runaway detecting system for detecting the runaway of a CPU in a CPU system comprising: resetter circuit means, activated by the turning ON of a power source of the CPU system or by a reset output signal of the CPU, for outputting a system reset signal to the CPU system to thereby reset the CPU, and first and second runaway detecting programs, operatively coupled to the CPU for controlling the CPU when they are activated by respective signals from corresponding first and second timers, the first runaway detecting program including error counting means for incrementally or decrementally changing an error count upon receipt of a periodic timer interrupt generated by the first timer and overflow-causing means for causing the second timer to overflow when the error count coincides with a predetermined value, the second runaway detecting program including reset signal generating means for generating said reset output signal to thereby reset the CPU either when said second runaway program timer overflows or when said second timer of the second runaway detecting program is restarted more than once before a predetermined period has elapsed.

Claim 4

A system for detecting the runaway of a CPU in a CPU system, comprising: resetting means for resetting the CPU either when power is initially applied to the CPU system or when a self-restarting output signal is generated by the CPU; and program means operatively coupled to the CPU to control said CPU, said program means including main loop means for cycling the CPU through a main loop of CPU operations, the main loop being capable of periodic interruption by an error count incrementing routine which increments an error count and the main loop means having an error count resetting means for resetting the error count with each successful cycling of the CPU through the main loop, said program means further having reset causing means for causing said self-restarting output signal to be outputted from said CPU when the main loop means fails to reset the error count within a predetermined loop time.

Claim 5

A system for detecting the runaway of a CPU in a CPU system, comprising: resetting means for resetting the CPU either when power is initially applied to the CPU system or when a self-restarting output signal is generated by the CPU; and program means operatively coupled to the CPU to control said CPU, said program means including main loop means for cycling the CPU through a main loop of CPU operations, the main loop being capable of periodic interruption by an error count incrementing routine which increments an error count and the main loop means having an error count resetting means for resetting the error count with each successful cycling of the CPU through the main loop, said program means further having reset causing means for causing said self-restarting output signal to be outputted from said CPU when the main loop means fails to reset the error count within a predetermined loop time.

Claim 10

A system for detecting and halting a runaway condition in a CPU comprising: main loop means for causing the CPU to cycle through a main loop of operations, being an error count reset operation which resets an error count; and first and second interrupt servicing means, operatively coupled to the CPU, for servicing interrupts generated by respective first and second timers, where the first timer generates interrupts periodically during the running of the main loop and where the second timer generates an overflow interrupt if a timer value thereof is allowed to increase with time from a reset value to an overflow value, wherein the second interrupt servicing means comprises reset means for generating a reset signal which causes the CPU to reset, and wherein the first interrupt servicing means comprises: second reset means for resetting the second timer, error count incrementing means for incrementing the error count away from its reset value, error count comparison means for determining whether the error count coincides with a preset value and for inhibiting the operation of the second reset means when such a coincidence occurs, and timer value comparison means for determining whether the value of the second timer is smaller than a predetermined set value and for activating the second interrupt servicing means if the second timer value is found at the time of determination to be smaller than the set value.

Claim 11

A system for detecting and halting a runaway condition in a CPU comprising: main loop means for causing the CPU to cycle through a main loop of operations, being an error count reset operation which resets an error count; and first and second interrupt servicing means, operatively coupled to the CPU, for servicing interrupts generated by respective first and second timers, where the first timer generates interrupts periodically during the running of the main loop and where the second timer generates an overflow interrupt if a timer value thereof is allowed to increase with time from a reset value to an overflow value, wherein the second interrupt servicing means comprises reset means for generating a reset signal which causes the CPU to reset, and wherein the first interrupt servicing means comprises: second reset means for resetting the second timer, error count incrementing means for incrementing the error count away from its reset value, error count comparison means for determining whether the error count coincides with a preset value and for inhibiting the operation of the second reset means when such a coincidence occurs, and timer value comparison means for determining whether the value of the second timer is smaller than a predetermined set value and for activating the second interrupt servicing means if the second timer value is found at the time of determination to be smaller than the set value.