US4902918A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable logic arrays with each array column divided into a plurality of series connections of FETs
Assignee: Toshiba Corp
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Filing: 1988-06-13
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Granted: 1990-02-20
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Expires: 2008-06-13
Abstract
Abstract Programmable logic arrays (PLAs) in the form of a matrix having each array column consisting of a plurality of FETs (Field Effect Transistors) in which cell arrays constituting each array column for producing logical product output signals are divided into a plurality of array blocks so as to reduce the number of the FETs to be connected in series in each array block and to eventually reduce the series resistance of each of the array columns, and the output signals from each of the array blocks thus divided are applied to the input terminals of each logical circuit so as to reduce each combined logical product from each logical gate, thereby realizing high speed operation for the PLAs.
Inventors
- 👤 Yukio Sugeno
- 👤 Kimiyoshi Usami
- 👤 Tohru Sasaki
- 👤 Yasuyuki Nozuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:00
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
142 words
A programmable logic array comprising: a set of input terminals; a plurality of first FETs arranged in columns in matrix form, said first FETs in each column of said columns being programmably coupled with said input terminals at their gate terminals, each of said columns being divided into a plurality of series connections of said first FETs, each of said series connections being connected to a higher logic level through a second FET at one end and to a lower logic level at the other end; and a plurality of OR gates having their input terminals connected, respectively, to said one end of each of said series connections in order to produce, as an output of said logic array, the logical sum of the logical levels at said one end of each of said series connections belonging to each of said columns.
Claim 2
Dependent Claim
142 words
A programmable logic array comprising: a set of input terminals; a plurality of first FETs arranged in columns in matrix form, said first FETs in each column of said columns being programmably coupled with said input terminals at their gate terminals, each of said columns being divided into a plurality of series connections of said first FETs, each of said series connections being connected to a higher logic level through a second FET at one end and to a lower logic level at the other end; and a plurality of OR gates having their input terminals connected, respectively, to said one end of each of said series connections in order to produce, as an output of said logic array, the logical sum of the logical levels at said one end of each of said series connections belonging to each of said columns.
Claim 3
Dependent Claim
19 words
The array of claim 1 wherein said input terminals are prepared to provide complementary pairs of logical input signals.
Claim 4
Dependent Claim
70 words
The array of claim 1 wherein said other end of each of said series connections is connected to said lower logic level through a third FET receiving a precharge signal at its gate terminal in order to be turned off by said precharge signal, and wherein the gate terminals of said second FETs are coupled to receive said precharge signal in order to be turned on by said precharge terminals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-19 | 1993-08-21 | 1994-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-19 | 1997-08-21 | 1998-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-19 | 2001-08-21 | 2002-02-20 | $7700.00 | Window Closed / Lapsed |