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US4902610A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for manufacture of multilayer circuit board

Assignee: Shipley Co Inc
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Filing: 1987-05-20
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Granted: 1990-02-20
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Expires: 2007-05-20
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Abstract

Abstract The invention is for the formation of multilayer circuit boards where layers are formed sequentially using selective plating techniques and photoimaging of permanent dielectric materials to achieve fine line resolution and interconnections between circuits. The invention permits the sequential formation of multilayers of higher density using photoimaging techniques.

Inventors

  • 👤 Charles R. Shipley

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 05:06
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4644; H05K3/465; H05K3/10; H05K3/20; H05K3/205; H05K3/4661; H05K3/4682; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09563; H05K2203/00; H05K2203/05; H05K2203/0562; H05K2203/0565; H05K2203/14; H05K2203/1407; H05K3/0011; H05K3/0017; H05K3/0023; H05K3/18; H05K3/181; H05K3/182; H05K3/184

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 196 words
A process for the formation of a multilayer printed circuit board, said process comprising the steps of providing a non-conductive carrier having a circuit pattern over at least one of its surfaces, applying a first permanent photo dielectric coating over the circuit pattern, exposing the permanent photo dielectric coating to activating radiation in an image pattern comprising an array of openings at locations where interconnections are desired and developing said imaged photo dielectric coating to provide photoformed openings, selectively providing an electroless plating catalyst within said photoformed openings and plating electroless copper onto said electroless plating catalyst to render the photoformed openings conductive, applying a permanent photo mask over the metalized layer of interconnections, exposing the permanent photo mask to activating radiation in an image pattern comprising an array of conductors and interconnections at desired locations, developing said imaged photo mask to provide photoformed conductor lines where conductors are desired and photoformed openings where interconnections are desired and selectively providing an electroless plating catalyst within said photoformed openings and plating electroless copper onto said electroless plating catalyst to render said photoformed openings conductive and repeating the process sequentially until the desired number of layers are formed.
Claim 2
Dependent Claim 196 words
A process for the formation of a multilayer printed circuit board, said process comprising the steps of providing a non-conductive carrier having a circuit pattern over at least one of its surfaces, applying a first permanent photo dielectric coating over the circuit pattern, exposing the permanent photo dielectric coating to activating radiation in an image pattern comprising an array of openings at locations where interconnections are desired and developing said imaged photo dielectric coating to provide photoformed openings, selectively providing an electroless plating catalyst within said photoformed openings and plating electroless copper onto said electroless plating catalyst to render the photoformed openings conductive, applying a permanent photo mask over the metalized layer of interconnections, exposing the permanent photo mask to activating radiation in an image pattern comprising an array of conductors and interconnections at desired locations, developing said imaged photo mask to provide photoformed conductor lines where conductors are desired and photoformed openings where interconnections are desired and selectively providing an electroless plating catalyst within said photoformed openings and plating electroless copper onto said electroless plating catalyst to render said photoformed openings conductive and repeating the process sequentially until the desired number of layers are formed.
Claim 3
Dependent Claim 23 words
The process of claim 1 where the photoformed openings for interconnections are in electrical communication with circuits on either side of the openings.
Claim 4
Dependent Claim 21 words
The process of claim 1, where deposited metal is retained by the walls of the openings into which it is plated.
Claim 5
Dependent Claim 32 words
The process of claim 1 where the electroless metal is plated to a thickness essentially the same as the thickness of the mask whereby the surface of the circuit is essentially planar.
Claim 6
Dependent Claim 29 words
The process of claim 1 including the step of separating multiple layers of circuits and interconnections with an innerlayer material having a ground and/or power plane on its surfaces.
Claim 7
Dependent Claim 31 words
The process of claim 1 including the step of laminating one or more stacks of multiple layers of circuits and interconnections to additional stacks of multiple layers of circuits and interconnections.
Claim 8
Dependent Claim 25 words
The process of claim 1 where the stacks are laminated using a B stage resin applied as a liquid and partially cured prior to stacking.

References Cited (Backward Citations)

US3573973A Cited
US3791858A Cited
US3799816A Cited
US4089686A Cited
US4107351A Cited
US4157407A Cited
US4528259A Cited
US4469777A Cited
US4567062A Cited
US4631111A Cited
US4572764A Cited
US4737446A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-02-19 1993-08-21 1994-02-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-02-19 1997-08-21 1998-02-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-02-19 2001-08-21 2002-02-20 $7700.00 Window Closed / Lapsed

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