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US4901035A Expired / Lapsed US ⏱️ 0.0 years remaining

Phase-locked loop control for reading data off storage media

Assignee: Aspen Peripherals Corp
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Filing: 1988-04-20
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Granted: 1990-02-13
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Expires: 2008-04-20
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Abstract

Abstract An improved phase-locked loop control having a phase detector receptive of a data preamble of all "ones" from a storage sub-system for producing early and late signals to a voltage controlled oscillator in order for the frequency of the oscillator to be synchronized with the frequency of the data. A pattern detector senses the incoming preamble pulses and prevents the generation of the early and late signals when a preamble pulse is not present within a predetermined window of time.

Inventors

  • 👤 Brian G. Cleveland

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 14:16
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/14; H03L7/085; H03L7/089

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 94 words
A phase-locked loop control having a phase detector (210) receptive of a data preamble of all "ones" from a storage sub-system (10, 30, 40, 50, 200) for producing early and late signals applied to a voltage controlled oscillator (220, 225, 230) in order for the frequency of said oscillator to be synchronized with the frequency of said data preamble, said phase detector comprising: means receptive of said data preamble for preventing the generation of said early and late signals when a preamble pulse (600) is not present within a predetermined window (W) of time.
Claim 2
Dependent Claim 94 words
A phase-locked loop control having a phase detector (210) receptive of a data preamble of all "ones" from a storage sub-system (10, 30, 40, 50, 200) for producing early and late signals applied to a voltage controlled oscillator (220, 225, 230) in order for the frequency of said oscillator to be synchronized with the frequency of said data preamble, said phase detector comprising: means receptive of said data preamble for preventing the generation of said early and late signals when a preamble pulse (600) is not present within a predetermined window (W) of time.
Claim 3
Dependent Claim 29 words
The phase-locked loop control of claim 1 wherein when the time between the start of one preamble pulse and the next is S, said window equals 0.5S to 1.5S.
Claim 4
Independent Claim 103 words
A method for a phase-locked loop control having a phase detector (210) receptive of a data preamble of all "ones" from a storage sub-system (10, 30, 40, 50, 200) for producing early and late signals applied to a voltage controlled oscillator (220, 225, 230) in order for the frequency of said oscillator to be synchronized with the frequency of said data preamble, said method comprising the steps of: sensing the presence of said "ones" in said data preamble, and preventing the generation of said early and late signals when a preamble pulse (600) is not present within a predetermined window (W) of time.
Claim 5
Independent Claim 103 words
A method for a phase-locked loop control having a phase detector (210) receptive of a data preamble of all "ones" from a storage sub-system (10, 30, 40, 50, 200) for producing early and late signals applied to a voltage controlled oscillator (220, 225, 230) in order for the frequency of said oscillator to be synchronized with the frequency of said data preamble, said method comprising the steps of: sensing the presence of said "ones" in said data preamble, and preventing the generation of said early and late signals when a preamble pulse (600) is not present within a predetermined window (W) of time.
Claim 6
Dependent Claim 28 words
The method of claim 3 wherein when the time between preamble the start of one preamble pulse and the next is S, said window equals 0.5S to 1.5S.
Claim 7
Independent Claim 124 words
A method for phase-locked loop control having a phase detector (210) receptive of a data preamble of all "ones" from a 3480 cartridge tape system (10, 30, 40, 50, 200) for producing early and late signals applied to a voltage controlled oscillator (220, 225, 230) during a high gain mode in order for the frequency of said oscillator to be synchronized with the frequency of said data preamble, said method comprising the steps of: sensing the presence of said "ones" in said data preamble during the high gain mode, and preventing the generation of said early and late signals when a preamble pulse (600) due to an error occurs before a counter reaches a first value or after the counter reaches a second value.
Claim 8
Independent Claim 124 words
A method for phase-locked loop control having a phase detector (210) receptive of a data preamble of all "ones" from a 3480 cartridge tape system (10, 30, 40, 50, 200) for producing early and late signals applied to a voltage controlled oscillator (220, 225, 230) during a high gain mode in order for the frequency of said oscillator to be synchronized with the frequency of said data preamble, said method comprising the steps of: sensing the presence of said "ones" in said data preamble during the high gain mode, and preventing the generation of said early and late signals when a preamble pulse (600) due to an error occurs before a counter reaches a first value or after the counter reaches a second value.

References Cited (Backward Citations)

US4068198A Cited
US4135163A Cited
US4360781A Cited
US4583053A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-02-12 1993-08-14 1994-02-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-02-12 1997-08-14 1998-02-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-02-12 2001-08-14 2002-02-13 $7700.00 Window Closed / Lapsed

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