Patent US4899351A successfully refreshed from Google Patents.
US4899351A
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Transient free clock switch logic
Assignee: Western Digital Corp
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Filing: 1988-07-18
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Granted: 1990-02-06
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Expires: 2008-07-18
Abstract
Abstract The invention provides a circuit for selecting a first clock, disabling a second or additional clocks and positively enabling the selected first clock only after the second or additional clocks no longer provide signal to the circuit.
Inventors
- 👤 Carl Bonke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:48
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0685; H04J3/0688
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
187 words
A clock switching circuit for selectively enabling first and second clocks comprising means for selecting the first or second clock, the selection means having a selection signal output; first means for synchronizing the selection signal output to the first clock; second means for synchronizing the selection signal output to the second clock; a first lock-out circuit having a first input responsive to the first synchronizer means; a second input responsive to the first clock, a third enabling input and an output providing a first clock enable signal; a second lock-out circuit having a first input responsive to the second synchronizer means; a second input responsive to the second clock; a third enabling input and an output providing a second clock enabling signal; a first delay circuit responsive to the second clock driven by the output of the first lockout circuit and having an output connected to the third input of the second lockout circuit; and, a second delay circuit responsive to the first clock driven by the output of the second lockout circuit and having an output connected to the third input of the first lockout circuit.
Claim 2
Dependent Claim
187 words
A clock switching circuit for selectively enabling first and second clocks comprising means for selecting the first or second clock, the selection means having a selection signal output; first means for synchronizing the selection signal output to the first clock; second means for synchronizing the selection signal output to the second clock; a first lock-out circuit having a first input responsive to the first synchronizer means; a second input responsive to the first clock, a third enabling input and an output providing a first clock enable signal; a second lock-out circuit having a first input responsive to the second synchronizer means; a second input responsive to the second clock; a third enabling input and an output providing a second clock enabling signal; a first delay circuit responsive to the second clock driven by the output of the first lockout circuit and having an output connected to the third input of the second lockout circuit; and, a second delay circuit responsive to the first clock driven by the output of the second lockout circuit and having an output connected to the third input of the first lockout circuit.
Claim 3
Dependent Claim
29 words
A clock switching circuit as defined in claim 1 further comprising: a sensor means for determining the enabled clock connected to the first lock-out circuit and second lock-out circuit;
Claim 4
Dependent Claim
21 words
A clock switching circuit as defined in claim 1 wherein each synchronizer means comprises at least two serially connected D-type flip-flops.
Claim 5
Dependent Claim
17 words
A clock switching circuit as defined in claim 1 wherein each lock-out circuit comprises a NOR flip-flop.
Claim 6
Dependent Claim
21 words
A clock switching circuit as defined in claim 1 wherein each delay circuit comprises at least two serially connected D-type flip-flops.
Claim 7
Dependent Claim
47 words
A clock switching circuit as defined in claim 1 further comprising means for resetting the selection means, first and second synchronizing means, first and second lock-out circuits, and first and second delay circuits to a predetermined state thereby selectively enabling the first clock as a default setting.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-05 | 1993-08-07 | 1994-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-05 | 1997-08-07 | 1998-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-05 | 2001-08-07 | 2002-02-06 | $7700.00 | Window Closed / Lapsed |