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US4899315A
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Low-power, noise-resistant read-only memory
Assignee: Texas Instruments Inc
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Filing: 1988-11-14
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Granted: 1990-02-06
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Expires: 2008-11-14
Abstract
Abstract A low-power, noise-resistant, read-only memory (10) is comprised of a plurality of array sections (14), each section (14) having a plurality of cell locations (70-86) arranged in rows (98) and columns (88-96). Each column (88-96) is provided with a virtual ground line (107-114). Bit lines (116-126) are shared between columns (88-96). In operation, the bit lines (116-126) and virtual ground lines (107-114) are pulled up to a high voltage state. Then, one selected virtual ground line (107-114) in each section (14) is pulled low to address a pair of cell locations (70, 72) in that section (14). No active pullup means are employed. The transmission of false data through a sneak path (550) is prevented by the actuation of disconnect circuitry (38) after allowing all valid data to be sensed.
Inventors
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:15
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/126
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
231 words
A memory including a plurality of rows and columns of memory cells, each row of memory being associated with a row address comprising a plurality of address bits, each row being capable of receiving a control signal through a word line, comprising: a row decoder for decoding an address of one of said rows, said row decoder comprising a plurality of NAND circuits, each NAND circuit being capable of receiving input from signals including a selected set of signals corresponding to a selected set consisting of address bits, complements of address bits or a combination thereof, each NAND circuit being further capable of outputting a plurality of signals received by selected word lines; each NAND circuit comprising a plurality of first transistors having current paths coupled in series between a voltage reference and a node, respective gates of said first transistors capable of receiving input from signals including a selected set of signals corresponding to a selected set consisting of address bits, complements of address bits or a combination thereof; a second transistor capable of having a current path for coupling said node to a selected signal output from a selected NAND circuit; and a third transistor having a current path for coupling said node to a signal selected from a set of signals corresponding to a selected set consisting of address bits, complements of address bits, or a combination thereof.
Claim 2
Dependent Claim
231 words
A memory including a plurality of rows and columns of memory cells, each row of memory being associated with a row address comprising a plurality of address bits, each row being capable of receiving a control signal through a word line, comprising: a row decoder for decoding an address of one of said rows, said row decoder comprising a plurality of NAND circuits, each NAND circuit being capable of receiving input from signals including a selected set of signals corresponding to a selected set consisting of address bits, complements of address bits or a combination thereof, each NAND circuit being further capable of outputting a plurality of signals received by selected word lines; each NAND circuit comprising a plurality of first transistors having current paths coupled in series between a voltage reference and a node, respective gates of said first transistors capable of receiving input from signals including a selected set of signals corresponding to a selected set consisting of address bits, complements of address bits or a combination thereof; a second transistor capable of having a current path for coupling said node to a selected signal output from a selected NAND circuit; and a third transistor having a current path for coupling said node to a signal selected from a set of signals corresponding to a selected set consisting of address bits, complements of address bits, or a combination thereof.
Claim 3
Dependent Claim
52 words
The decoder of claim 1, wherein said NAND circuit is capable of receiving an enabling signal, and wherein the decoder further comprises a transistor responsive to said enabling signal, said transistor being operable such that said transistor is coupled in series with selected first transistors between said node and said voltage reference.
References Cited (Backward Citations)
US3895360A
Cited
US3971001A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-05 | 1993-08-07 | 1994-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-05 | 1997-08-07 | 1998-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-05 | 2001-08-07 | 2002-02-06 | $7700.00 | Window Closed / Lapsed |