Patent US4899066A successfully refreshed from Google Patents.
US4899066A
Expired / Lapsed
US
⏱️ 0.0 years remaining
OR-type CMOS logic circuit with fast precharging
Assignee: Mitsubishi Electric Corp
•
Filing: 1986-04-07
•
Granted: 1990-02-06
•
Expires: 2006-04-07
Abstract
Abstract A complementary metal oxide semiconductor logic circuit comprises a signal line OR-connecting a plurality of MOS transistors which are turned on/off by a plurality of decoder outputs. The signal line is divided by a MOS-FET in two portions including a portion on an output side provided with an inverter and an OR-connected transistors side, so that respective portions of the signal line as divided are precharged by separate precharging MOS transistors.
Inventors
- 👤 Masatoshi Aikawa
- 👤 Hiromasa Nakagawa
- 👤 Tsunenori Umeki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:43
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
221 words
An OR-type CMOS logic circuit with fast precharging comprising: a single data line having a first portion and a second portion; a plurality of MOS transistors connected to said first portion of said single data line in a wired OR manner, said plurality of MOS transistors operative in response to address decode signals; inverter means connected to said second portion of said single data line for outputting a signal on said second portion of said single data line; an MOS transistor connected to the input of said inverter for stabilizing an input signal of said inverter means, said MOS transistor operative in response to the output of said inverter; a first precharging MOS transistor connected to said first portion of said single data line for precharging said first portion of said single data line to a predetermined level in response to a precharging signal; a second precharging MOS transistor connected to said second portion of said single data line for precharging said second portion of said single data line to said predetermined level in response to said precharging signal; and an isolating MOS transistor interposed between said first and second portions of said single data line for isolating said first portion of said single data line from said second portion of said single data line in response to said precharging signal.
Claim 2
Dependent Claim
221 words
An OR-type CMOS logic circuit with fast precharging comprising: a single data line having a first portion and a second portion; a plurality of MOS transistors connected to said first portion of said single data line in a wired OR manner, said plurality of MOS transistors operative in response to address decode signals; inverter means connected to said second portion of said single data line for outputting a signal on said second portion of said single data line; an MOS transistor connected to the input of said inverter for stabilizing an input signal of said inverter means, said MOS transistor operative in response to the output of said inverter; a first precharging MOS transistor connected to said first portion of said single data line for precharging said first portion of said single data line to a predetermined level in response to a precharging signal; a second precharging MOS transistor connected to said second portion of said single data line for precharging said second portion of said single data line to said predetermined level in response to said precharging signal; and an isolating MOS transistor interposed between said first and second portions of said single data line for isolating said first portion of said single data line from said second portion of said single data line in response to said precharging signal.
Claim 3
Dependent Claim
22 words
A CMOS logic circuit in accordance with claim 1, wherein said first precharging MOS transistor comprises an n-channel MOS field effect transistor.
Claim 4
Dependent Claim
22 words
A CMOS logic circuit in accordance with claim 1, wherein said second precharging MOS transistor comprises a p-channel MOS field effect transistor.
Claim 5
Dependent Claim
22 words
A CMOS logic circuit in accordance with claim 1, wherein said CMOS logic circuit is formed on a semiconductor integrated circuit device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-05 | 1993-08-07 | 1994-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-05 | 1997-08-07 | 1998-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-05 | 2001-08-07 | 2002-02-06 | $7700.00 | Window Closed / Lapsed |