Patent US4897702A successfully refreshed from Google Patents.
US4897702A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device and manufacturing method for the same
Assignee: Toshiba Corp
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Filing: 1988-02-24
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Granted: 1990-01-30
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Expires: 2008-02-24
Abstract
Abstract An isolated region in which a MOS transistor and a capacitor are formed is surrounded by a groove. The groove includes first and second region grooves. A first insulating layer which separates the isolated region is provided on the inner surface of a predetermined lower portion of the first region groove and on the inner surface of the second region groove. A second insulating layer is provided on the inner surface of the remaining upper portion of the first region groove. The first insulating layer is thinner than half the width of the groove and thicker than the first insulating layer. A capacitor electrode is embedded in the first and second region grooves.
Inventors
- 👤 Kazumasa Sunouchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:33
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/30; H10B12/37; H10B12/02; H10B12/03; H10B12/038
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
196 words
A semiconductor memory device comprising groove means formed in a semiconductor substrate for separating one memory cell-forming region from another, said memory cell comprising a MOS transistor formed in said memory cell-forming region and a capacitor connected in series to said MOS transistor, and said groove means including a first groove in which a first insulating layer for separating said memory cell-forming region and a second insulating layer for forming said capacitor are formed, and a second groove in which said first insulating layer is formed; wherein said first insulating layer in said first groove is formed on the inner surface of a predetermined lower portion of said first groove and has a thickness which is less than half the width of said first groove, said second insulating layer has a thickness which is less than that of said first insulating layer, said second insulating layer in said first groove is provided on the inner surface of the remaining upper portion of said first groove, and a capacitor electrode is made of semiconductor material provided in said first groove along said first and second insulating layers and in said second groove, along said first insulating layer.
Claim 2
Dependent Claim
196 words
A semiconductor memory device comprising groove means formed in a semiconductor substrate for separating one memory cell-forming region from another, said memory cell comprising a MOS transistor formed in said memory cell-forming region and a capacitor connected in series to said MOS transistor, and said groove means including a first groove in which a first insulating layer for separating said memory cell-forming region and a second insulating layer for forming said capacitor are formed, and a second groove in which said first insulating layer is formed; wherein said first insulating layer in said first groove is formed on the inner surface of a predetermined lower portion of said first groove and has a thickness which is less than half the width of said first groove, said second insulating layer has a thickness which is less than that of said first insulating layer, said second insulating layer in said first groove is provided on the inner surface of the remaining upper portion of said first groove, and a capacitor electrode is made of semiconductor material provided in said first groove along said first and second insulating layers and in said second groove, along said first insulating layer.
Claim 3
Dependent Claim
24 words
A semiconductor memory device according to claim 1, wherein said semiconductor substrate is made of silicon and said capacitor electrode is made of polysilicon.
Claim 4
Dependent Claim
181 words
A semiconductor memory device comprising groove means formed in a semiconductor substrate of a first conductive type for electrically separating one memory cell-forming region from another, said memory cell comprising a MOS transistor formed in said memory cell-forming region and a capacitor connected in series to said MOS transistor, and said groove means including a capacitor forming groove in which said capacitor is formed, wherein said capacitor forming groove includes a first insulating layer provided on the inner surface of a predetermined lower portion of said capacitor forming groove, and a second insulating layer provided on the inner surface of the remaining upper portion of said capacitor forming groove of a second conductivity type, said first insulating layer has a thickness which is less than half the width of said capacitor forming groove, providing a recess in said lower portion of said capacitor forming groove, and said first insulating layer being thicker than that of said second insulating layer, and a capacitor electrode made of semiconductor material is provided in said capacitor forming groove along said first and second insulating layers.
Claim 5
Dependent Claim
181 words
A semiconductor memory device comprising groove means formed in a semiconductor substrate of a first conductive type for electrically separating one memory cell-forming region from another, said memory cell comprising a MOS transistor formed in said memory cell-forming region and a capacitor connected in series to said MOS transistor, and said groove means including a capacitor forming groove in which said capacitor is formed, wherein said capacitor forming groove includes a first insulating layer provided on the inner surface of a predetermined lower portion of said capacitor forming groove, and a second insulating layer provided on the inner surface of the remaining upper portion of said capacitor forming groove of a second conductivity type, said first insulating layer has a thickness which is less than half the width of said capacitor forming groove, providing a recess in said lower portion of said capacitor forming groove, and said first insulating layer being thicker than that of said second insulating layer, and a capacitor electrode made of semiconductor material is provided in said capacitor forming groove along said first and second insulating layers.
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JPS61156859A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-29 | 1993-07-31 | 1994-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-29 | 1997-07-31 | 1998-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-29 | 2001-07-31 | 2002-01-30 | $7700.00 | Window Closed / Lapsed |