Patent US4896298A successfully refreshed from Google Patents.
US4896298A
Expired / Lapsed
US
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Read circuit for memory
Assignee: STMicroelectronics SA
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Filing: 1988-01-25
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Granted: 1990-01-23
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Expires: 2008-01-25
Abstract
Abstract A read circuit is disclosed for logic circuit type integrated circuits comprising a memory consisting of a matrix of memory cells. The memory cells are each addressable by rows and columns selected by row and column decoders. The read circuit, which is connected to the memory cells by a line called a bit line, comprises a pre-loading circuit for the bit line and a detection circuit that detects the discharging or non-discharging of the bit line depending on whether the memory cell selected is in the state "0" or "1", and also comprises a means to memorize the state that is read. The circuit further comprises means which make it possible, in read mode, to discharge the bit line regardless of whether the memory cell is in the state "1" or "0" and means that delay the moment of discharge. The invention can be applied to EPROMs or similar memories.
Inventors
- 👤 Jacek Kowalski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 02:00
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/24; G11C16/26; G11C7/00; G11C7/24
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
138 words
A reading circuit for a matrix of memory cells, said cells being arranged in rows and columns, the cells belonging to a common column being connected to a common corresponding bit line, said circuit comprising: a precharge circuit for precharging said bit line to a precharge voltage prior to a reading operation; and a detection circuit connected to said bit line and activated by a reading signal, said detection circuit detecting the discharge of said precharge bit line during a read operation and said discharge being dependant upon the logical state of an addressed cell of said memory cells which addressed cell is connected to said bit line and said reading circuit further comprising means for systematically discharging said bit line after the read operation whether or not said bit line has been discharged during the read operation.
Claim 2
Dependent Claim
138 words
A reading circuit for a matrix of memory cells, said cells being arranged in rows and columns, the cells belonging to a common column being connected to a common corresponding bit line, said circuit comprising: a precharge circuit for precharging said bit line to a precharge voltage prior to a reading operation; and a detection circuit connected to said bit line and activated by a reading signal, said detection circuit detecting the discharge of said precharge bit line during a read operation and said discharge being dependant upon the logical state of an addressed cell of said memory cells which addressed cell is connected to said bit line and said reading circuit further comprising means for systematically discharging said bit line after the read operation whether or not said bit line has been discharged during the read operation.
Claim 3
Dependent Claim
38 words
A reading circuit according to claim 1, wherein said means for systematically discharging the bit line comprises a transistor connected to the bit line and capable of being rendered conductive by an enabling signal following said reading signal.
Claim 4
Dependent Claim
48 words
A reading circuit according to claim 2, further comprising a transistor connected between said bit line and said detection circuit, said transistor being rendered conductive during said read operation and being rendered non-conductive by said enabling signal output from said means for a systematically discharging said bit line.
Claim 5
Dependent Claim
49 words
A reading circuit according to claim 1, further comprising a capacitor connected in series with said cell, between said bit line and a ground supply terminal, and a means for short-circuiting said capacitor prior to said read operation and for allowing charging of said capacitor during said read operation.
Claim 6
Dependent Claim
29 words
A reading circuit according to claim 4 wherein said means for short circuiting the capacitor comprises a transistor activated by a short-circuiting signal occurring prior to said read operation.
Claim 7
Dependent Claim
21 words
A reading circuit according to claim 5, wherein said short-circuiting signal occurs substantially simultaneous with the precharging of said bit line.
Claim 8
Dependent Claim
25 words
A reading circuit according to claim 4, wherein said capacitor has a capacitance of at least approximately ten times the capacitance of said bit line.
Claim 9
Dependent Claim
21 words
A reading circuit according to claim 4, wherein said capacitor is common to the cells of one or more bit lines.
References Cited (Backward Citations)
US4475178A
Cited
US4545038A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-22 | 1993-07-24 | 1994-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-22 | 1997-07-24 | 1998-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-22 | 2001-07-24 | 2002-01-23 | $7700.00 | Window Closed / Lapsed |