FET overtemperature protection circuit

Claim 2

A FET overtemperature protection circuit comprising: a FET having at least gate, source and drain electrodes, one of the drain and source electrodes intended for connection to a load so that the FET can selectively control current supplied to the load; drive excitation circuit means for providing excitation to the FET to selectively control conduction of the FET in accordance with received control signals; first circuit means coupled to the FET for developing a first signal indicative of and varying in accordance with the voltage between the FET drain and source electrodes; second circuit means coupled to the FET for developing a second signal indicative of and varying in accordance with current flowing through one of said FET drain and source electrodes when said FET is on; combining circuit means coupled to the first and second circuit means for receiving the first and second signals and combining them to provide an output signal in response thereto when a predetermined relationship exists between the first and second signals indicative of FET drain to source on resistance exceeding a predetermined value; and coupling means for providing said output signal as at least one of the control input signals received by said drive excitation circuit means, said drive excitation means including means for responding to said output signal by reducing said FET current when said predetermined relationship exsits.

Claim 3

A protection circuit according to claim 1 wherein said combining circuit means comprises a comparator which provides said output signal when said first signal has a magnitude which exceeds the magnitude of said second signal by a predetermined amount.

Claim 4

A protection circuit according to claim 1 which includes short circuit protection means coupled to said FET for providing a short circuit control signal to said driver excitation circuit means for reducing the FET current when FET current exceeds some predetermined threshold.

Claim 5

A protection circuit according to claim 3 wherein said short circuit protection means includes a comparator which receives the second signal, compares it to a predetermined threshold and provides the short circuit control signal in response to this comparison.

Claim 6

A protection circuit according to claim 1 wherein said first and second circuit means each comprise differential amplifier circuits.

Claim 7

A protection circuit according to claim 1 wherein said FET comprises a current sensing FET having at least gate, drain, source and current mirror electrodes.

Claim 8

A protection circuit according to claim 6 wherein said FET also includes a Kelvin electrode, and wherein the protection circuit includes a current sensing resistor connected between the mirror and Kelvin electrodes with the Kelvin electrode directly connected to the FET source electrode.

Claim 9

A protection circuit according to claim 7 wherein said second circuit means includes a differential amplifier connected across said current sensing resistor means to provide said second signal.

Claim 10

A protection circuit according to claim 1 wherein said second circuit means includes a current sensing resistor coupled to said FET for receiving current from said FET and developing thereacross a voltage related to the current flowing through said one of said FET drain and source electrodes when said FET is on.

Claim 11

A protection circuit according to claim 9 wherein a differential amplifier circuit is connected across said FET, the output of said differential amplifier circuit corresponding to said second signal.

Claim 12

A protection circuit according to claim 10 wherein said first circuit means comprises a differential amplifier circuit having one input coupled to the source electrode of said FET and another input connected to the drain electrode of said FET, said differential amplifier providing providing at an output terminal said first signal.

Claim 13

A protection circuit according to claim 11 wherein the outputs of the differential amplifiers in said first and second means are coupled as inputs to a comparator circuit included in said combining circuit means which provides at the output of this comparator said output signal.

Claim 14

A protection circuit according to claim 1 which includes start up circuit means coupled to said drive excitation circuit means for providing a start up signal for preventing said output signal from reducing said FET current for a predetermined time after the FET is initially turned on by a control signal received by said drive excitation circuit means.

Claim 15

A protection circuit according to claim 13 which includes short circuit protection means coupled to said FET for providing a short circuit control signal to said driver excitation circuit means for reducing the FET current when FET current exceeds some predetermined threshold.

Claim 16

A protection circuit according to claim 14 wherein said drive excitation circuit means includes a gate circuit means having said short circuit and output signals coupled as inputs thereto and providing a single output in response thereto for control of said FET.

Claim 17

A protection circuit according to claim 1 wherein said drive circuit means includes for turning said FET off in response to said one of said control signals provided by said coupling means.

Claim 18

A FET overtemperature protection circuit comprising: a FET having at least gate, source and drain electrodes; a load, one of the FET drain and source electrodes connected to said load for the FET selectively supplying FET through current to the load; drive excitation circuit means for providing excitation to the FET to selectively control conduction of the FET in accordance with received control signals; first circuit means coupled to the FET for developing a first signal indicative of and varying in accordance with the voltage between the FET drain and source electrodes; second circuit means coupled to the FET for developing a second signal indicaative of and varying in accordance with current flowing through one of said FET drain and source electrodes when said FET is on; combining circuit means coupled to the first and second circuit means for receiving the first and second signals and combining them to provide an output signal in response thereto when a predetermined relationship exists between the first and second signals indicative of FET drain to source on resistance exceeding a predetermined value; and coupling means for providing said output signal as at least one of the control input signals received by said drive excitation circuit means, said drive excitation means including means for responding to said output signal by reducing said FET current when said predetermined relationship exists.

Claim 19

A FET overtemperature protection circuit comprising: a FET having at least gate, source and drain electrodes; a load, one of the FET drain and source electrodes connected to said load for the FET selectively supplying FET through current to the load; drive excitation circuit means for providing excitation to the FET to selectively control conduction of the FET in accordance with received control signals; first circuit means coupled to the FET for developing a first signal indicative of and varying in accordance with the voltage between the FET drain and source electrodes; second circuit means coupled to the FET for developing a second signal indicaative of and varying in accordance with current flowing through one of said FET drain and source electrodes when said FET is on; combining circuit means coupled to the first and second circuit means for receiving the first and second signals and combining them to provide an output signal in response thereto when a predetermined relationship exists between the first and second signals indicative of FET drain to source on resistance exceeding a predetermined value; and coupling means for providing said output signal as at least one of the control input signals received by said drive excitation circuit means, said drive excitation means including means for responding to said output signal by reducing said FET current when said predetermined relationship exists.

Claim 20

A protection circuit according to claim 17 wherein said combining circuit means comprises a comparator which provides said output signal when said first signal has a magnitude which exceeds the magnitude of said second signal by a predetermined amount.

Claim 21

A protection circuit according to claim 18 which includes short circuit protection means coupled to said FET current for providing a short circuit control signal to said driver excitation circuit means for reducing the FET current when FET current exceeds some predetermined threshold.

Claim 22

A protection circuit according to claim 19 which includes start up circuit means coupled to said drive excitation circuit means for providing a start up signal for preventing said output signal from reducing said FET current for a predetermined time after the FET is initially turned on by a control signal received by said drive excitation circuit means.

Claim 23

A transistor overtemperature protection circuit comprising: a transistor having a least a control electrode and two separate main current conduction electrodes the current therethrough dependent on signals at said control electrode, one of the current conduction electrodes intended for connection to a load so that the transistor can selectively control current supplied to the load; drive excitation circuit means for providing excitation to the transistor to selectively control conduction of the transistor in accordance with received control signals; first circuit means coupled to the transistor for developing a first signal indicative of and varying in accordance with the voltage between the transistor current conduction electrodes; second circuit means coupled to the transistor for developing a second signal indicative of and varying in accordance with current flowing through one of said current conduction electrodes when said transistor is on; combining circuit means coupled to the first and second circuit means for receiving the first and second signals and combining them to provide an output signal in response thereto when a predetermined relationship exists between the first and second signals indicative of transistor on resistance between said current conduction electrodes exceeding a predetermined value; and coupling means for providing said output signal as at least one of the control input signals received by said drive excitation circuit means, said drive excitation means including means for responding to said output signal by reducing said transistor current through said current conduction electrodes when said predetermined relationship exists.

Claim 24

A transistor overtemperature protection circuit comprising: a transistor having a least a control electrode and two separate main current conduction electrodes the current therethrough dependent on signals at said control electrode, one of the current conduction electrodes intended for connection to a load so that the transistor can selectively control current supplied to the load; drive excitation circuit means for providing excitation to the transistor to selectively control conduction of the transistor in accordance with received control signals; first circuit means coupled to the transistor for developing a first signal indicative of and varying in accordance with the voltage between the transistor current conduction electrodes; second circuit means coupled to the transistor for developing a second signal indicative of and varying in accordance with current flowing through one of said current conduction electrodes when said transistor is on; combining circuit means coupled to the first and second circuit means for receiving the first and second signals and combining them to provide an output signal in response thereto when a predetermined relationship exists between the first and second signals indicative of transistor on resistance between said current conduction electrodes exceeding a predetermined value; and coupling means for providing said output signal as at least one of the control input signals received by said drive excitation circuit means, said drive excitation means including means for responding to said output signal by reducing said transistor current through said current conduction electrodes when said predetermined relationship exists.