Resetting arrangement for a semiconductor integrated circuit device having semiconductor memory

Claim 2

A static memory comprising: a plurality of static type memory cells which store data therein; a plurality of word lines and a plurality of pairs of complementary data lines coupled to said plurality of memory cells so that each static type memory cell is coupled to a word line and a pair of complementary data lines; and selecting means coupled to said plurality of word lines including decoder means responsive to address signals for selecting one of said plurality of word lines and further including simultaneous selection means responsive to a control signal for simultaneously bringing predetermined word lines into a selection state.

Claim 3

A static memory according to claim 1, wherein each of said plurality of static type memory cells comprises a flip-flop circuit including a pair of N-channel MOSFETs having gates and drains thereof cross-coupled and load elements coupled to the drains of said pair of N-channel MOSFETs.

Claim 4

A static memory according to claim 1, wherein said load elements comprises resistor elements comprised of a polycrystalline silicon film.

Claim 5

A static memory according to claim 2, wherein said load elements comprise P-channel MOSFETs each of which has a source-drain path coupled to the drain of the corresponding N-channel MOSFET.

Claim 6

A static memory according to claim 4, further comprising: supply means coupled to said plurality of pairs of complementary data lines and including first means for supplying a first voltage to one of the respective pair of complementary data lines and second means for supplying a second voltage to the other of the respective pair of complementary data lines, said first voltage being lower than said second voltage, wherein said simultaneous selection means in said selecting means brings said predetermined word lines into a selection state under a state where said first and second voltages are supplied to the respective pair of complementary data lines.

Claim 7

A static memory according to claim 5, further comprising: a first terminal to which a third voltage substantially identical with said first voltage is supplied; and a second terminal to which a fourth voltage substantially identical with said second voltage is supplied, wherein said first means includes first MOSFETs each of which has its source-drain path thereof coupled between said first terminal and one of the pair of complementary data lines, and wherein said second means includes second MOSFETs each of which has its source-drain path thereof coupled between said second terminal and the other of the pair of complementary data lines.

Claim 8

A static memory according to claim 6, wherein said first MOSFETs are N-channel MOSFETs, and wherein said second MOSFETs are P-channel MOSFETs.

Claim 9

A static memory according to claim 6, wherein both said first and second MOSFETs are N-channel MOSFETs.

Claim 10

A static memory according to claim 1, wherein a static memory cell coupled to one of said predetermined word lines and a static memory cell coupled to another one of said predetermined word lines are both coupled to one pair of complementary data lines of said pairs of complementary data lines.

Claim 11

A microcomputer including an arithmetic logic unit and a static memory coupled to said arithmetic logic unit via a bus, said static memory comprising: a plurality of static type memory cells which store data therein; a plurality of word lines and a plurality of pairs of complementary data lines coupled to said plurality of static type memory cells so that each static type memory cell is coupled to a word line and a pair of complementary data lines; and selecting means coupled to said plurality of word lines including decoder means responsive to address signals for selecting one of said plurality of word lines and further including simultaneous selection means responsive to a control signal for simultaneously bringing predetermined word lines into a selection state so that data stored in static type memory cells which are coupled to said predetermined word lines can be set at identical data.

Claim 12

A microcomputer including an arithmetic logic unit and a static memory coupled to said arithmetic logic unit via a bus, said static memory comprising: a plurality of static type memory cells which store data therein; a plurality of word lines and a plurality of pairs of complementary data lines coupled to said plurality of static type memory cells so that each static type memory cell is coupled to a word line and a pair of complementary data lines; and selecting means coupled to said plurality of word lines including decoder means responsive to address signals for selecting one of said plurality of word lines and further including simultaneous selection means responsive to a control signal for simultaneously bringing predetermined word lines into a selection state so that data stored in static type memory cells which are coupled to said predetermined word lines can be set at identical data.

Claim 13

A microcomputer according to claim 10, wherein said static memory is formed in a register group.

Claim 14

A microcomputer according to claim 10, wherein each of said plurality of static type memory cells comprises a flip-flop including a pair of inverters each of which has an N-channel MOSFET connected in series with a load element, said two inverters being cross-coupled with respect to their input and output, and a transmission MOSFET for coupling the input/output of the flip-flop to the complementary data line.

Claim 15

A microcomputer according to claim 12, wherein said load element is a resistor comprised of a polycrystalline silicon film.

Claim 16

A microcomputer according to claim 12, wherein said load element is a P-channel MOSFET having its gate coupled to a gate of said N-channel MOSFET.

Claim 17

A microcomputer according to claim 10, further comprising: supply means coupled to said plurality of pairs of complementary data lines and including first means for supplying a first voltage to one of the respective pair of complementary data lines and second means for supplying a second voltage to the other of the respective pair of complementary data lines, said first voltage being lower than said second voltage, wherein said simultaneous selection means in said selecting means brings said predetermined word lines into a selection state under a state where said first and second voltages are supplied to the respective pair of complementary data lines.

Claim 18

A microcomputer according to claim 15, wherein said first means includes a first MOSFET having its source-drain path connected in series with one of the respective pair of complementary data lines, and wherein said second means include a second MOSFET having its source-drain path connected in series with the other of the respective pair of complementary data lines.

Claim 19

A microcomputer according to claim 16, wherein said first and second MOSFETs are N-channel type MOSFETs.

Claim 20

A microcomputer according to claim 16, wherein said first MOSFET is an N-channel type MOSFET, and wherein said second MOSFET is a P-channel type MOSFET.

Claim 21

A static memory according to claim 10, wherein a static memory cell coupled to one of said predetermined word lines and a static memory cell coupled to another one of said predetermined word lines are both coupled to one pair of complementary data lines of said pairs of complementary data lines.

Claim 22

An MOS static memory formed in a register group in a computer, said MOS static memory comprising: a plurality of static type memory cells which store data therein; a plurality of word lines and a plurality of pairs of complementary data lines coupled to said plurality of static type memory cells so that each static type memory cell is coupled to a word line and a pair of complementary data lines; and selecting means coupled to said plurality of word lines including decoder means responsive to address signals for selecting one of said plurality of word lines and further including simultaneous selection means responsive to a control signal for simultaneously bringing predetermined word lines into a selection state so that data stored in static type memory cells which are coupled to said predetermined word lines can be set at identical data.

Claim 23

An MOS static memory formed in a register group in a computer, said MOS static memory comprising: a plurality of static type memory cells which store data therein; a plurality of word lines and a plurality of pairs of complementary data lines coupled to said plurality of static type memory cells so that each static type memory cell is coupled to a word line and a pair of complementary data lines; and selecting means coupled to said plurality of word lines including decoder means responsive to address signals for selecting one of said plurality of word lines and further including simultaneous selection means responsive to a control signal for simultaneously bringing predetermined word lines into a selection state so that data stored in static type memory cells which are coupled to said predetermined word lines can be set at identical data.

Claim 24

An MOS static memory according to claim 20, wherein each of said plurality of static type memory cells comprises a flip-flop including a pair of inverters each of which has an N-channel MOSFET connected in series with a load element, said two inverters being cross-coupled with respect to their input and output, and a transmission MOSFET for coupling the input/output of the flip-flop to the complementary data line.

Claim 25

An MOS static memory according to claim 21, wherein said load element is a resistor comprised of a polycrystalline silicon film.

Claim 26

An MOS static memory according to claim 21, wherein said load element is a P-channel MOSFET having its gate coupled to a gate of said N-channel MOSFET.

Claim 27

An MOS static memory according to claim 20, further comprising: supply means coupled to said plurality of pairs of complementary data lines and including first means for supplying a first voltage to one of the respective pair of complementary data lines and second means for supplying a second voltage to the other of the respective pair of complementary data lines, said first voltage being lower than said second voltage, wherein said simultaneous selection means in said selecting means brings said predetermined word lines into a selection state under a state where said first and second voltages are supplied to the respective pair of complementary data lines.

Claim 28

An MOS static memory according to claim 24, wherein said first means includes a first MOSFET having its source-drain path connected in series with one of the respective pair of complementary data lines, and wherein said second means includes a second MOSFET having its source-drain connected in series with the other of the respective pair of complementary data lines.

Claim 29

An MOS static memory according to claim 25, wherein said first and second MOSFETs are N-channel type MOSFETs.

Claim 30

An MOS static memory according to claim 25, wherein said first MOSFET is an N-channel type MOSFET, and wherein said second MOSFET is a P-channel type MOSFET.

Claim 31

A static memory according to claim 20, wherein a static memory cell coupled to one of said predetermined word lines and a static memory cell coupled to another one of said predetermined word lines are both coupled to one pair of complementary data lines of said pairs of complementary data lines.

Claim 32

In a microcomputer implemented in a semiconductor integrated circuit device, said microcomputer comprising an arithmetic logic unit and data registers coupled to said arithmetic logic unit via bus means for transmitting data between said arithmetic logic unit and said data registers, said data registers being constructed of an MOS static memory, said MOS static memory comprising: a plurality of static type memory cells each of which store data therein; a plurality of word lines and a plurality of pairs of data lines coupled to said plurality of static memory cells so that each static type memory cell is coupled to a word line and a pair of data lines; and selecting means coupled to said plurality of word lines including decoder means responsive to address signals for selecting one of said plurality of word lines in accordance with said address signals and further including simultaneous selection means responsive to a first control signal for simultaneously bringing predetermined word lines into a selection state in accordance with said control signal.

Claim 33

In a microcomputer implemented in a semiconductor integrated circuit device, said microcomputer comprising an arithmetic logic unit and data registers coupled to said arithmetic logic unit via bus means for transmitting data between said arithmetic logic unit and said data registers, said data registers being constructed of an MOS static memory, said MOS static memory comprising: a plurality of static type memory cells each of which store data therein; a plurality of word lines and a plurality of pairs of data lines coupled to said plurality of static memory cells so that each static type memory cell is coupled to a word line and a pair of data lines; and selecting means coupled to said plurality of word lines including decoder means responsive to address signals for selecting one of said plurality of word lines in accordance with said address signals and further including simultaneous selection means responsive to a first control signal for simultaneously bringing predetermined word lines into a selection state in accordance with said control signal.

Claim 34

In a mocrocomputer according to claim 29, further comprising: potential setting means coupled to said pair of data lines and responsive to a second control signal for setting potential levels of said predetermined pair of data lines so that the potential level of one of said predetermined pair of data lines is set at a predetermined high level and the potential level of the other of said predetermined pair of data lines is set at a predetermined low level in accordance with said second control signal, wherein said simultaneous selection means in said selecting means brings said predetermined word lines into the selection state under a state where said potential setting means set the potential levels of said predetermined pair of data lines at the predetermined high and low levels, respectively.

Claim 35

A static memory according to claim 29, wherein a static memory cell coupled to one of said predetermined word lines and a static memory cell coupled to another one of said predetermined word lines are both coupled to one pair of complementary data lines of said pairs of complementary data lines.