Patent US4894705A successfully refreshed from Google Patents.
US4894705A
Expired / Lapsed
US
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Semiconductor device
Assignee: Sharp Corp
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Filing: 1987-09-24
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Granted: 1990-01-16
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Expires: 2007-09-24
Abstract
Abstract A semiconductor device has high-resistance polysilicon sections sandwiched between two wiring layers. Low-resistance sections are formed by ion-injection of impurities across selected ones of these high-resistance polysilicon sections to electrically connect the two wiring layers according to a user's specification.
Inventors
- 👤 Setsufumi Kamuro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:22
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491; H10W20/492
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
95 words
A semiconductor device comprising a first wiring layer, a second wiring layer, an inter-layer insulative film between said first wiring layer and said second wiring layer, and a plurality of polysilicon sections sandwiched between said first and second wiring layers, different ones of said polysilicon sections being separated by said inter-layer insulative film, selected ones of said polysilicon sections being low-resistance polysilicon sections and the rest of said polysilicon sections being high-resistance polysilicon sections such that said first and second wiring layers are electrically connected with each other through each of said low-resistance polysilicon sections.
Claim 2
Dependent Claim
95 words
A semiconductor device comprising a first wiring layer, a second wiring layer, an inter-layer insulative film between said first wiring layer and said second wiring layer, and a plurality of polysilicon sections sandwiched between said first and second wiring layers, different ones of said polysilicon sections being separated by said inter-layer insulative film, selected ones of said polysilicon sections being low-resistance polysilicon sections and the rest of said polysilicon sections being high-resistance polysilicon sections such that said first and second wiring layers are electrically connected with each other through each of said low-resistance polysilicon sections.
Claim 3
Dependent Claim
13 words
The semiconductor device of claim 1 wherein said low-resistance polysilicon sections contain impurities.
Claim 4
Dependent Claim
24 words
The semiconductor device of claim 1 further comprising a semiconductor substrate and an insulating layer between said semiconductor substrate and said second wiring layer.
Claim 5
Dependent Claim
13 words
The semiconductor device of claim 1 wherein said second wiring layer comprises aluminum.
Claim 6
Dependent Claim
19 words
The semiconductor device of claim 1 wherein said second wiring layer comprises a metal with a high melting point.
Claim 7
Dependent Claim
18 words
The semiconductor device of claim 1 wherein said high-resistance polysilicon sections have a specific resistance of about 100Ω/square.
Claim 8
Dependent Claim
18 words
The semiconductor device of claim 1 wherein said high-resistance polysilicon sections are of P-type and include N-type impurities.
Claim 9
Dependent Claim
19 words
The semiconductor device of claim 1 wherein said low-resistance polysilicon sections have specific resistance in the range of 10-100GΩ/square.
Claim 10
Dependent Claim
16 words
The semiconductor device of claim 1 further comprising a protective layer covering said first wiring layer.
Claim 11
Dependent Claim
22 words
The semiconductor device of claim 1 wherein said first and second wiring layers each comprise a plurality of mutually parallel metallic lines.
Claim 12
Dependent Claim
16 words
The semiconductor device of claim 3 wherein said low-resistance polysilicon sections are of N 30 -type.
References Cited (Backward Citations)
US4546366A
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US4297721A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |