US4894568A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate control circuit for a switching power MOS transistor
Assignee: STMicroelectronics SA
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Filing: 1989-02-02
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Granted: 1990-01-16
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Expires: 2009-02-02
Abstract
Abstract A gate control circuit for a power MOS transistor (1), the first main electrode (D) of which is connected to a high voltage (V CC ) through a load (L), the second main electrode (S) of which is grounded and the gate (G) of which is connected, during the switching ON period, to a low voltage source (V DD ), comprises a switch (S1) for connecting at the switching ON of the power MOS transistor its first main electrode to its gate.
Inventors
- 👤 Antoine Pavlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:16
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/68; H03K17/04; H03K17/042; H03K17/04206; H03K17/041; H03K17/0412; H03K17/04123; H03K17/567; H03K17/687; H03K17/6877
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
83 words
A gate control circuit for a power MOS transistor (1), the first main electrode of which (D) is connected to a high current voltage (V CC ) through a load (L), the second main electrode of which (S) is grounded and the gate (G) of which is connected, during the switching ON period, to a low voltage source (V DD ), comprising switching means (S1) for connecting, at the switching On of said power MOS transistor, said first main electrode to said gate.
Claim 2
Dependent Claim
83 words
A gate control circuit for a power MOS transistor (1), the first main electrode of which (D) is connected to a high current voltage (V CC ) through a load (L), the second main electrode of which (S) is grounded and the gate (G) of which is connected, during the switching ON period, to a low voltage source (V DD ), comprising switching means (S1) for connecting, at the switching On of said power MOS transistor, said first main electrode to said gate.
Claim 3
Dependent Claim
86 words
A gate control circuit according to claim 1, wherein the power MOS transistor (1) is a VDMOS-type realized in a semiconductor substrate where a vertical bipolar transistor (T) is also formed, the rear face of the substrate corresponding to the VDMOS drain and to the bipolar transistor collector, said drain (D) constituting said first main electrode, wherein the bipolar transistor emitter is connected to the VDMOS transistor gate and wherein its base receives the switching ON signal (C) at the same time as the VDMOS gate.
Claim 4
Dependent Claim
20 words
A gate control circuit according to claim 2, wherein said emitter is connected to said gate through a resistor (R).
Claim 5
Dependent Claim
36 words
A gate control circuit according to claim 2, comprising means (42 ; 63, 64) for blocking the conduction of the bipolar transistor as soon as the drain voltage of the VDMOS is approaching its gate voltage.
Claim 6
Dependent Claim
35 words
A gate control circuit according to claim 2, wherein the voltages of the VDMOS gate and of the bipolar transistor base are supplied through bootstrap logic circuits (40, 41) in response to a control signal.
References Cited (Backward Citations)
US3515905A
Cited
DE1762420A1
Cited
US3740581A
Cited
US4256978A
Cited
US4663547A
Cited
US4480201A
Cited
DE3405936A1
Cited
DE3617610A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |