Patent US4893233A successfully refreshed from Google Patents.
US4893233A
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Method and apparatus for dynamically controlling each stage of a multi-stage pipelined data unit
Assignee: NXP USA Inc
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Filing: 1988-04-18
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Granted: 1990-01-09
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Expires: 2008-04-18
Abstract
Abstract A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.
Inventors
- 👤 Denman Marvin A.
- 👤 Yoav Talgam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
237 words
In a pipelined data unit for use in a data processor, a data unit comprising: an input stage for selectively receiving input operands from said data processor; a plurality of operation stages for performing selected operations on said input operands to produce an output result, at least a first one of said operation stages, coupled to said input stage, for performing its respective operation in one of a plurality of ways as selected by a value of a control signal; an output stage, coupled to at least a last one of said operation stages, for selectively providing said output result to said data processor; instruction buffer means, substantially coincident with said plurality of operation stages, for providing to each of said plurality of operation stages selected information related to a respective one of a plurality of instructions executing in said plurality of operation stages; and control means, coupled to said plurality of operation stages, for controlling execution of said instructions in each of said plurality of operation stages in accordance with the information relating thereto provided by said instruction buffer means; the improvement comprising: control signal buffer means, coupled to said instruction buffer means, for storing, for each of said instructions, a corresponding value of said control signal, and providing said corresponding value of said control signal to said first one of said operation stages substantially coincident with said instruction buffer means providing the corresponding instruction information.
Claim 2
Dependent Claim
237 words
In a pipelined data unit for use in a data processor, a data unit comprising: an input stage for selectively receiving input operands from said data processor; a plurality of operation stages for performing selected operations on said input operands to produce an output result, at least a first one of said operation stages, coupled to said input stage, for performing its respective operation in one of a plurality of ways as selected by a value of a control signal; an output stage, coupled to at least a last one of said operation stages, for selectively providing said output result to said data processor; instruction buffer means, substantially coincident with said plurality of operation stages, for providing to each of said plurality of operation stages selected information related to a respective one of a plurality of instructions executing in said plurality of operation stages; and control means, coupled to said plurality of operation stages, for controlling execution of said instructions in each of said plurality of operation stages in accordance with the information relating thereto provided by said instruction buffer means; the improvement comprising: control signal buffer means, coupled to said instruction buffer means, for storing, for each of said instructions, a corresponding value of said control signal, and providing said corresponding value of said control signal to said first one of said operation stages substantially coincident with said instruction buffer means providing the corresponding instruction information.
Claim 3
Dependent Claim
72 words
The data unit of claim 1 wherein at least a second one of said operation stages provides a status signal, whereby a status signal value indicates a selected condition of the instruction executing in said second one of said operation stages; and wherein the control signal buffer means also store, for each of said instructions, the value of said status signal, and selectively provides said stored status value to said data processor.
Claim 4
Dependent Claim
231 words
In a pipelined data unit for use in a data processor, a data unit comprising: an input stage for selectively receiving input operands from said data processor; a plurality of operation stages for performing selected operations on said input operands to produce an output result, at least one of said operation stages, coupled to said input stage, for performing its respective operation in one of a plurality of ways as selected by a value of a control signal; an output stage, coupled to at least a last one of said operation stages, for selectively providing said output result to said data processor; instruction buffer means, substantially coincident with said plurality of operation stages, for providing to each of said plurality of operation stages selected information related to a respective one of a plurality of instructions executing in said plurality of operation stages; and control means, coupled to said plurality of operation stages, for controlling execution of said instructions in each of said plurality of operation stages in accordance with the information relating thereto provided by said instruction buffer means; a method for dynamically controlling said data unit, comprising the steps of: storing, for each of said instructions, a corresponding value of said control signal; and providing said stored value to at least a first one of said operation stages substantially coincident with said instruction buffer means providing the corresponding instruction information.
Claim 5
Dependent Claim
231 words
In a pipelined data unit for use in a data processor, a data unit comprising: an input stage for selectively receiving input operands from said data processor; a plurality of operation stages for performing selected operations on said input operands to produce an output result, at least one of said operation stages, coupled to said input stage, for performing its respective operation in one of a plurality of ways as selected by a value of a control signal; an output stage, coupled to at least a last one of said operation stages, for selectively providing said output result to said data processor; instruction buffer means, substantially coincident with said plurality of operation stages, for providing to each of said plurality of operation stages selected information related to a respective one of a plurality of instructions executing in said plurality of operation stages; and control means, coupled to said plurality of operation stages, for controlling execution of said instructions in each of said plurality of operation stages in accordance with the information relating thereto provided by said instruction buffer means; a method for dynamically controlling said data unit, comprising the steps of: storing, for each of said instructions, a corresponding value of said control signal; and providing said stored value to at least a first one of said operation stages substantially coincident with said instruction buffer means providing the corresponding instruction information.
Claim 6
Dependent Claim
66 words
The method of claim 3 further comprising the step of: providing a status signal from a second one of said operation stages, whereby a status signal value indicates a selected condition of the instruction executing in said second one of said operation stages; and wherein the value of said status signal, for each of said instructions, is also stored and selectively provided to said data processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-08 | 1993-07-10 | 1994-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-08 | 1997-07-10 | 1998-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-08 | 2001-07-10 | 2002-01-09 | $7700.00 | Window Closed / Lapsed |