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US4893166A Expired / Lapsed US ⏱️ 0.0 years remaining

High value semiconductor resistor

Assignee: Vishay Siliconix Inc
•
Filing: 1989-02-21
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Granted: 1990-01-09
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Expires: 2009-02-21
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Abstract

Abstract In accordance with the teachings of this invention, resistors are fabricated in semiconductor devices utilizing a layer of semiconductor material having a preselected resistivity. Means are provided for electrically isolating the semiconductor region from the regions located beneath, and isolation to adjacent regions is provided by forming a groove. Resistance value of a particular resistor fabricated in accordance with the teachings of this invention is dependent, in a coarse fashion, on the length and width of the resistor, as well as the resistivity of the semiconductor material used to fabricate the resistor. However, the final resistance value is determined by the diffusion of high concentration isolation dopants which serve to accurately control the effective cross-sectional area of the resistor. Once the rough physical dimensions of a resistor have been established, its actual resistance value is controlled very closely by, for example, introducing isolation dopants, diffusing the isolation dopants for a specified period of time, measuring a resistance value and, if necessary, further diffusing the isolation dopants. This iterative process of diffusing isolation dopants and measuring resistance value is repeated as required in order to fabricate resistors of desired resistance values.

Inventors

  • 👤 James Geekie

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 19:01
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/43

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 142 words
A semiconductor structure comprising: a sublayer formed of semiconductor material of a first conductivity type; a semiconductor layer of said first conductivity type formed on said sublayer; a groove formed in said semiconductor layer substantially to said sublayer, thereby forming an island of said semiconductor layer; a peripheral region of said island of said semiconductor layer, formed as the top and sides of said island, said peripheral region being doped to a second conductivity type opposite said first conductivity type; and an isolation region formed in said sublayer beneath said island of semiconductor material, said isolation region being of said second conductivity type, whereby a central portion of said island remains doped to said first conductivity type, whereby said central portion of said island serves as a resistor and said peripheral portion of said island is junction isolated from said central portion.
Claim 2
Dependent Claim 142 words
A semiconductor structure comprising: a sublayer formed of semiconductor material of a first conductivity type; a semiconductor layer of said first conductivity type formed on said sublayer; a groove formed in said semiconductor layer substantially to said sublayer, thereby forming an island of said semiconductor layer; a peripheral region of said island of said semiconductor layer, formed as the top and sides of said island, said peripheral region being doped to a second conductivity type opposite said first conductivity type; and an isolation region formed in said sublayer beneath said island of semiconductor material, said isolation region being of said second conductivity type, whereby a central portion of said island remains doped to said first conductivity type, whereby said central portion of said island serves as a resistor and said peripheral portion of said island is junction isolated from said central portion.
Claim 3
Dependent Claim 13 words
A semiconductor structure as in claim 1, wherein said sublayer is semiconductive material.
Claim 4
Dependent Claim 26 words
A semiconductor structure as in claim 1 wherein said semiconductor layer has an impurity concentration in the range of approximately 5×10 14 to 8×10 16 atoms/cc.
Claim 5
Dependent Claim 26 words
A semiconductor structure as in claim 3, wherein said peripheral region has an impurity concentration in the range of approximately 5×10 16 to 1×10 20 .
Claim 6
Dependent Claim 27 words
A semiconductor structure as in claim 1, wherein the resistance of said island of semiconductor material is determined in part by the extent of said peripheral region.
Claim 7
Dependent Claim 19 words
A semiconductor structure as in claim 1, including a contact region formed to make electrical contact with said island.
Claim 8
Dependent Claim 17 words
A semiconductor structure as in claim 6, including an electrical interconnect making connection with said contact region.
Claim 9
Dependent Claim 23 words
A semiconductor structure as in claim 7, wherein said electrical interconnect is formed within said groove over at least part of its length.
Claim 10
Dependent Claim 14 words
A semiconductor structure as in claim 1, including an insulation layer over said island.
Claim 11
Dependent Claim 20 words
A semiconductor structure as in claim 1, wherein said peripheral region is adjacent the top and sides of said island.

References Cited (Backward Citations)

JPS551103A Cited
JPS62150873A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-01-08 1993-07-10 1994-01-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-01-08 1997-07-10 1998-01-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-01-08 2001-07-10 2002-01-09 $7700.00 Window Closed / Lapsed

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