One or more input asynchronous register

Claim 2

A register comprising: an output flip-flop having set and reset inputs and at least one output signal line; a first gating means for applying an input signal D and its complement D respectively to said reset and set inputs under control of a switching edge of an applied input load control signal L, said first gating means operating such that said input signal D and its complement D are applied to said reset and set inputs, upon occurrence of a predetermined switching edge of said load control signal only for a period of time sufficient to cause a switching of the state of the output state of said flip-flop by one of said D and D signals, said period ending when at least one feedback signal, responsive to said state switching, indicates by a predetermined switching edge that said state switching has occurred.

Claim 3

A register as in claim 1 wherein said first gating means comprises: a first pair of OR gates respectively receiving said D and D signals as inputs thereto, the output of one said OR gate being connected to said reset input and the output os the other of said OR gates being connected to said set input; and a first pair of switching circuits, each having an output Y which changes state upon a change of state of an applied input signal at a signal input X, with said output Y reverting to its original state in response to a predetermined switching edge in a said feed back signal applied at another input, said pair of switching circuits having said load control signal applied in common to the X signal inputs thereof and respective outputs which are connected to respective inputs of said pair of OR gates.

Claim 4

A register as in claim 1 wherein said first gating means further comprises: a plurality of n, where n is an integer, pairs of OR gates, each pair of OR gates respectively receiving D n and complemented D n signals as inputs thereto, the output of one of the OR gates of each pair being connected to a respective reset input of said output flip-flop and the output of the other of said OR gates of each pair being connected to a respective set input of said output flip-flop, a plurality of n pairs of switching circuits, each having an output Y which changes state upon a change of state of an applied input signal at a signal input X, with said output Y reverting to its original state in response to a predetermined switching edge in a said feedback signal applied at another input, each pair of said switching circuits having one of a plurality of load control signals L n applied in common to the X signal inputs thereof and respective outputs connected to respective inputs of an associated pair of OR gates receiving the D n and D n signals.

Claim 5

A register as in claim 3 wherein an output signal Q(1) of said output flip-flop is defined by the logical equation: ##EQU9## where Q is the complemented output of the output Q(1) of said output flip-flop, D i and D i are the respective D and D inputs for each of said pairs of OR gates, L i is the respective common load control signal for each pair of switching circuits, P Si and P Ri are respective internal signal states of switching circuits respectively controlling application of the D i and D i signals to set and reset inputs of said output flip-flop, represents a logical AND function, V represents a logical OR function and represents a logical AND function.

Claim 6

A register as in claim 2 wherein each of said switching circuits has a respective feedback signal applied thereto, one of said feedback signals being taken from said output signal line, and the other being a complement of the signal on said output signal line.

Claim 7

A register as in claim 2 wherein a single feedback signal is applied in common to said pair of switching circuits.

Claim 8

A register as in claim 6 wherein said output flip-flop is formed by a pair of cross-coupled logical gates, said register further comprising a second gating means for generating said common feedback signal, said second gating means comprising a first XOR gate having one input connected to an output of a first of said cross-coupled logical gates and another input connected to an output of one of said OR gates, a second XOR gate having one input connected to an output of a second of said cross-coupled logical gates and another input connected to an output of the other of said OR gates, and another OR gate receiving the outputs of said first and second XOR gates and providing said common feedback signal at its output.

Claim 9

A register as in claim 3 wherein first and second feedback signals are produced at said output flip-flop, one of said feedback signals being taken from said output signal line, and the other being a complement of the signal on said output signal line, one of the switching circuits of each pair of switching circuits receiving said first feedback signal and the other of the switching circuits of each pair of switching circuits receiving said second feedback signal.

Claim 10

A register as in claim 3 wherein a single feedback signal is produced which is applied in common to all of said switching circuits.

Claim 11

A register as in claim 9 wherein said output flip-flop is formed by a pair of cross-coupled logical gates, said register further comprising a second gating means for producing said common feedback signal, said second gating means comprising a first plurality of XOR gates, each having one input connected to an output of one of said cross-coupled logical gates and another input respectively connected to an output of a first OR gate of a respective pair of OR gates, a second plurality of XOR gates each having one input connected to an output of the other of said cross-coupled logical gates and another input respectively connected to an output of second OR gate of a respective pair of OR gates, the outputs of said XOR gates being applied to another OR gate which produces said common feedback signal.

Claim 12

A register as in claim 1, wherein said first gating means comprises: a first switching circuit including a first output gate, an output signal of said first output gate being connected to one of said set and reset inputs of said output flip-flop, said first switching circuit having at least three inputs, a first for receiving a data D input signal, a second for receiving a load control signal L, and a third for receiving a feedback signal which changes state upon a change in state of said output flip-flop; and, a second switching circuit including a second output gate, an output signal of said second output gate being connected to the other of said set and reset inputs of said output flip-flop, said second switching circuit having at least three inputs, a first for receiving an inverted data D input signal, a second for receiving said load control signal L and a third for receiving a feedback signal which changes state upon a change in state of said output flip-flop, said first and second switching circuits operating such that one of said data signals D and D is applied to a respective reset and set input of said output flip-flop through said first or second output gates upon the occurrence of said predetermined switching edge of said load control signal only for said period of time, said period of time ending when that switching circuit applying the D or D signal to said output flip-flop detects said predetermined switching edge in an associated feedback signal indicating a change of state of said output flip-flop.

Claim 13

A register as in claim 11 wherein each of said first and second output gates is a NAND gate.

Claim 14

A register in claim 12 wherein each said output NAND gate has a first input for receiving one of said data signals D and D, a second input for receiving an applied load signal L, and a third input for receiving the output of an associated control flip-flop, said control flip-flop for said first switching circuit respectively receiving at first and second inputs thereto said applied data signal D and load control signal L, and at a third input a said feedback signal, said control flip-flop for said second switching circuit receiving at first and second inputs thereto said applied data signal D and load control signal L, and at a third input a said feedback signal.

Claim 15

An register as in claim 13 wherein said first output NAND gate has an input for receiving the feedback signal applied to the control flip-flop for said first switch circuit and said second output NAND gate has an input for receiving the feedback signal applied to the control flip-flop for said second switching circuit.

Claim 16

A register as in claim 13 wherein a single feedback signal is applied in common to said first and second output NAND gates.

Claim 17

A register as in claim 15 wherein said output flip-flop is formed by a pair of cross-coupled logical gates, said register further comprising a second gating means for generating said common feedback signal, said second gating means comprising a first XOR gate having one input respectively connected to an output of a first of said cross-coupled logical gates and a second input connected to an output of one of said NAND gates, a second XOR gate having one input connected to an output of a second of said cross-coupled logical gates and another input connected to the output of the other of said output NAND gates, and an OR gate receiving the outputs of said first and second XOR gates and providing said common feedback signal at its output.

Claim 18

A register as in claim 11 wherein said first gating means further comprises: a plurality of pairs of said first and second switching circuits, each of said pairs of first and second switching circuits respectively receiving one of a plurality of applied data signal D N and an associated one of a plurality of applied load control signal L N and applying one of its data D N or complement D N signal to an associated reset or set input of said output flip-flop in response to a switching edge of its associated load control signal L N , only for said period of time which ends when the switching circuit applying the D N or D N signal to said output flip-flop detects a switching edge in an associated feedback signal indicating a change of state of said output flip-flop.

Claim 19

A register as in claim 13 further comprising: a plurality of pairs of said first and second switching circuits, each pair having respective first and second switching circuits, each pair having respective first and second output NAND gates, each of said pairs of first and second switching circuits respectively receiving one of a plurality of applied data signals D N and an associated one of a plurality of applied load control signal L N and applying one of its data D N or complement D N signal to an associated reset or set input of said output flip-flop in response to a switching edge of its associated load control signal L N , only for said period of time which ends when the switching circuit applying the D N or D N signal to said output flip-flop detects a switching edge in an associated feedback signal indicating a change of state of said output flip-flop.

Claim 20

A register as in claim 18 wherein the feedback signal for one of the switching circuits of each pair of switching circuits is taken from a first output of said output flip-flop while the feedback signal for the output of the other of the switching circuits of each pair of switching circuits is taken from a complement of the first output of said output flip-flop.

Claim 21

A register as in claim 18 wherein a single feedback signal is applied in common to all of said switching circuits.

Claim 22

A register as in claim 20 wherein said output flip-flop is formed by a pair of cross-coupled logical gates and further comprising a second gating means for producing said common feedback signal, said second gating means comprising a first plurality of XOR gates, each having one input connected to an output of one of said cross-coupled logical gates and another input respectively connected to an output of a first output NAND gate of a respective pair of said switching circuits, a second plurality of XOR gates each having one input connected to an output of the other of said cross-coupled logical gates and another input respectively connected to an output of a second output NAND gate of a respective pair of switching circuits, the outputs of said XOR gates being applied to an OR gate which produces said common feedback signal.

Claim 23

A register as in claim 4 wherein each of said switching circuits changes state upon a change of state of an applied input signal X only when said feedback signal F is in a predetermined state and said output signal Q(1) is defined by the logical equation: ##EQU10## and the feedback signal logical equation is: ##EQU11## where S i =D i L i P Si F and R i =D i L i P Ri F, where Q is the complement of output signal Q(1) of said output flip-flop, D i and D i are the respective D and D inputs for each of said pairs of OR gates, L i is the respective common load control signal for each pair of switching circuits, and P Si and P Ri are respective internal signal states of switching circuits respectively controlling application of the D i and D i signals to the set and reset inputs of said output flip-flop.

Claim 24

A register as in claim 18 wherein the output signal Q(1) of said output flip-flop is defined by the logical equation: ##EQU12## where Q is the output of said output flip-flop, D i and D i are the respective D and D inputs for the first and second output NAND gates of each pair of switching circuits, L i is the respective common load control signal for each pair of switching circuits, and P Si and P Ri are respective internal signal states of switching circuits respectively controlling application of D i and D i signals to the set and reset inputs of said output flip-flop.

Claim 25

A register as in claim 23 wherein each of said switching circuits changes state upon occurrence of said predetermined switching edge of an applied load signal only when said feedback signal F is in a predetermined state and said output signal Q(1) is defined by the logical equation: ##EQU13## and the feedback signal logical equation is: ##EQU14## where S i =D i L i P Si F and R i =D i L i P Ri F, where Q is the complement of output signal Q(1) of said output flip-flop, D i and D i are the respective D and D inputs for each of said pairs of output NAND gates, L i is the respective common load control signal for each pair of switching circuits, and P Si and P Ri are respective internal signal states of switching circuits respectively controlling application of the D i and D i signals to the set and reset inputs of said output flip-flop.

Claim 26

A register as in claim 1 further comprising means for placing said output flip-flop in one of a CLEAR state and a PRESET state.