US4891729A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated-circuit apparatus
Assignee: Fujitsu Ltd
•
Filing: 1989-03-20
•
Granted: 1990-01-02
•
Expires: 2009-03-20
Abstract
Abstract A semiconductor integrated-circuit apparatus includes a electro-conductive layer formed on a substrate, a plurality of internal cells formed on the electro-conductive layer, a plurality of bonding pads arranged around the internal cells, and a plurality of bias cells which are common to the plurality of internal cells and which generate a predetermined voltage. A plurality of bias buffer circuits supply the predetermined voltage generated in the bias cells to the internal cells.
Inventors
- 👤 Eiji Sugiyama
- 👤 Mitsuaki Natsume
- 👤 Toshiharu Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/003; H03K19/00307; H03K19/08; H03K19/082; H03K19/086; H03K19/17704; H03K19/1778; H03K19/17784; H03K19/17796; H10; H10D; H10D84/00; H10D84/90; H10D84/901
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
348 words
An integrated circuit device formed on a substrate having a conduction layer formed therein, comprising: a first power supply line formed on said substrate; a second power supply line formed on said substrate having a voltage different from a voltage of said first power supply line; a plurality of ECL gate cells formed on said substrate, each of said ECL gate cells comprising: a pair of emitter coupled transistors having a base, having an emitter and having a collector, the collector of said emitter coupled transistors being operatively connected to said first power supply line; a current source means, connected between the emitters of said emitter coupled transistors and said second power supply line; and an output transistor having a base operatively connected to the collector of said emitter coupled transistors, having an emitter, and having a collector operatively connected to said first power supply line; a plurality of input-output pads formed on said substrate and selectively connected to the base of one of said emitter coupled transistors and to the emitter of said output transistor through the conduction layer formed on the substrate; and a plurality of electrostatic preventing means formed on the substrate and adjacent to said input-output pads respectively, each of said electrostatic preventing means including an electrostatic preventing element and a resistor, said electrostatic preventing means connected to one of said input-output pads such that when one of said input-output pads is connected to the base of one of said emitter coupled transistors said electrostatic preventing element is connected between one of said input-output pads and said first power supply line and said resistor is connected between one of said input-output pads and the base of one of said emitter coupled transistors, and when one of said input-output pads is connected to the emitter of said output transistor said electrostatic preventing element is connected between said one of said input-output pads and said first power supply line, the emitter of said output transistor being connected to said one of said input-output pads and said resistor not connected to said one of said input-output pads.
Claim 2
Dependent Claim
348 words
An integrated circuit device formed on a substrate having a conduction layer formed therein, comprising: a first power supply line formed on said substrate; a second power supply line formed on said substrate having a voltage different from a voltage of said first power supply line; a plurality of ECL gate cells formed on said substrate, each of said ECL gate cells comprising: a pair of emitter coupled transistors having a base, having an emitter and having a collector, the collector of said emitter coupled transistors being operatively connected to said first power supply line; a current source means, connected between the emitters of said emitter coupled transistors and said second power supply line; and an output transistor having a base operatively connected to the collector of said emitter coupled transistors, having an emitter, and having a collector operatively connected to said first power supply line; a plurality of input-output pads formed on said substrate and selectively connected to the base of one of said emitter coupled transistors and to the emitter of said output transistor through the conduction layer formed on the substrate; and a plurality of electrostatic preventing means formed on the substrate and adjacent to said input-output pads respectively, each of said electrostatic preventing means including an electrostatic preventing element and a resistor, said electrostatic preventing means connected to one of said input-output pads such that when one of said input-output pads is connected to the base of one of said emitter coupled transistors said electrostatic preventing element is connected between one of said input-output pads and said first power supply line and said resistor is connected between one of said input-output pads and the base of one of said emitter coupled transistors, and when one of said input-output pads is connected to the emitter of said output transistor said electrostatic preventing element is connected between said one of said input-output pads and said first power supply line, the emitter of said output transistor being connected to said one of said input-output pads and said resistor not connected to said one of said input-output pads.
Claim 3
Dependent Claim
16 words
An integrated circuit device according to claim 1, wherein said electrostatic preventing element comprises a diode.
Claim 4
Dependent Claim
16 words
An integrated circuit device according to claim 1, wherein said electrostatic preventing element comprises a transistor.
References Cited (Backward Citations)
US4580063A
Cited
US4517476A
Cited
US4763184A
Cited
US4689504A
Cited
US4811155A
Cited
US4791521A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-01 | 1993-07-03 | 1994-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-01 | 1997-07-03 | 1998-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-01 | 2001-07-03 | 2002-01-02 | $7700.00 | Window Closed / Lapsed |