Circuit for comparing magnitudes of binary signals

Claim 2

A circuit for comparing first and second binary signals, comprising: a first n-channel MOS transistor having a gate electrode to which the first binary signal is applied; a second n-channel MOS transistor having a source electrode connecting to a source electrode of said first MOS transistor, and a gate electrode to which a third binary signal different in logical level from the first binary signal is applied; a third n-channel MOS transistor having a source electrode connecting to a drain electrode of said first MOS transistor, and a gate electrode to which the second binary signal is applied; a fourth n-channel MOS transistor having a source electrode connecting to a drain electrode of said second MOS transistor, and a gate electrode to which a fourth binary signal different in logical level from the second binary signal is applied; an output port connected to a drain electrode of said third MOS transistor and a drain electrode of said fourth MOS transistor; a fifth n-channel MOS transistor having a drain electrode connecting to the drain electrode of said first MOS transistor and the source electrode of said third MOS transistor, a gate electrode to which the third binary signal is applied, and a source electrode maintained at ground; and an element for supplying a supply voltage to the drain electrode of said second MOS transistor and the source electrode of said fourth transistor.

Claim 3

A circuit as claimed in claim 1, wherein when the first and second binary signals are different in logical level from each other, said second MOS transistor, said third MOS transistor and said fifth MOS transistors are turned on and said first MOS transistor and said fourth MOS transistor are turned off or said second MOS transistor, said third MOS transistor and said fifth MOS transistor are turned off and said first MOS transistor and said fourth MOS transistor are turned on and, when the first and second binary signals are equal in logical level to each other, said second MOS transistor and said fourth MOS transistor are turned on or said first MOS transistor and said third MOS transistor are turned on.

Claim 4

A circuit as claimed in claim 1, wherein an auxiliary input signal is applied to the source of said second MOS transistor and the source of said first MOS transistor.

Claim 5

A circuit as claimed in claim 1, wherein said supplying element comprises a p-channel MOS transistor.

Claim 6

A circuit as claimed in claim 1, wherein said supplying element means comprises a load MOS transistor.

Claim 7

A circuit as claimed in claim 1, wherein said supplying element comprises a resistor.

Claim 8

A circuit for comparing first and second N-bit binary signals where N is a non-zero positive integer, comprising N 1-bit comparing circuits each comprising: a first n-channel MOS transistor having a gate electrode to which a first binary signal is applied; a second n-channel MOS transistor having a source electrode connecting to a source electrode of said first MOS transistor, and a gate electrode to which a third binary signal different in logical level from the first binary signal is applied; a third n-channel MOS transistor having a source electrode connecting to a drain electrode of said first MOS transistor, and a gate electrode to which a second binary signal is applied; a fourth n-channel MOS transistor having a source electrode connecting to a drain electrode of said second MOS transistor, and a gate electrode to which a fourth binary signal different in logical level from the second binary signal is applied; an output port connected to a drain electrode of said third MOS transistor and a drain electrode of said fourth MOS transistor; an auxiliary input port connected to the source electrode of said first MOS transistor and the source electrode of said second MOS transistor; a fifth n-channel MOS transistor having a drain electrode connecting to the drain electrode of said first MOS transistor and the source electrode of said third MOS transistor, a gate electrode to which the third binary signal is applied, and a source electrode maintained at ground; and an element for supplying a supply voltage to the drain electrode of said second MOS transistor and the source electrode of said fourth MOS transistor; said 1-bit comparing circuits being cascaded in N consecutive stages with said output ports and said auxiliary input ports of said 1-bit comparing circuits adjacent to each other being connected to each other; and each bit of said first N-bit binary signal being supplied as said first binary signal to each of said N 1-bit comparing circuits on the gate electrode of said first n-channel MOS transistor while each bit of said second N-bit binary signal being supplied as said second binary signal to each of said N 1-bit comparing circuits on the gate electrode of said third n-channel MOS transistor.

Claim 9

A circuit for comparing first and second N-bit binary signals where N is a non-zero positive integer, comprising N 1-bit comparing circuits each comprising: a first n-channel MOS transistor having a gate electrode to which a first binary signal is applied; a second n-channel MOS transistor having a source electrode connecting to a source electrode of said first MOS transistor, and a gate electrode to which a third binary signal different in logical level from the first binary signal is applied; a third n-channel MOS transistor having a source electrode connecting to a drain electrode of said first MOS transistor, and a gate electrode to which a second binary signal is applied; a fourth n-channel MOS transistor having a source electrode connecting to a drain electrode of said second MOS transistor, and a gate electrode to which a fourth binary signal different in logical level from the second binary signal is applied; an output port connected to a drain electrode of said third MOS transistor and a drain electrode of said fourth MOS transistor; an auxiliary input port connected to the source electrode of said first MOS transistor and the source electrode of said second MOS transistor; a fifth n-channel MOS transistor having a drain electrode connecting to the drain electrode of said first MOS transistor and the source electrode of said third MOS transistor, a gate electrode to which the third binary signal is applied, and a source electrode maintained at ground; and an element for supplying a supply voltage to the drain electrode of said second MOS transistor and the source electrode of said fourth MOS transistor; said 1-bit comparing circuits being cascaded in N consecutive stages with said output ports and said auxiliary input ports of said 1-bit comparing circuits adjacent to each other being connected to each other; and each bit of said first N-bit binary signal being supplied as said first binary signal to each of said N 1-bit comparing circuits on the gate electrode of said first n-channel MOS transistor while each bit of said second N-bit binary signal being supplied as said second binary signal to each of said N 1-bit comparing circuits on the gate electrode of said third n-channel MOS transistor.

Claim 10

A circuit for comparing first and second binary signals comprising: first, second, third, fourth and fifth n-channel MOS transistors; the sources of said first and second MOS transistors connected at a first common node; the drain of said second MOS transistor and the source of said fourth MOS transistor being connected at a second common node; the drains of said third and fourth MOS transistors being connected at a third common node; the drains of said first and fifth MOS transistors and the source of said third MOS transistor being connected at a fourth common node; first and second input terminals connected to the gates of said first and third MOS transistors, respectively, for inputting said first and second binary signals, respectively; means for providing third and fourth binary signals to the respective gates of said second and fourth MOS transistors, respectively, said third and fourth binary signals respectively being different in logical level from said first and second binary signals an output terminal connected to said third common node; a power terminal for connecting the circuit to an external power source providing a supply voltage, said power terminal being connected within said circuit to an element for supplying said supply voltage to said second common mode; and a ground terminal for connecting the source of said fifth MOS transistor to ground.

Claim 11

A circuit for comparing first and second binary signals comprising: first, second, third, fourth and fifth n-channel MOS transistors; the sources of said first and second MOS transistors connected at a first common node; the drain of said second MOS transistor and the source of said fourth MOS transistor being connected at a second common node; the drains of said third and fourth MOS transistors being connected at a third common node; the drains of said first and fifth MOS transistors and the source of said third MOS transistor being connected at a fourth common node; first and second input terminals connected to the gates of said first and third MOS transistors, respectively, for inputting said first and second binary signals, respectively; means for providing third and fourth binary signals to the respective gates of said second and fourth MOS transistors, respectively, said third and fourth binary signals respectively being different in logical level from said first and second binary signals an output terminal connected to said third common node; a power terminal for connecting the circuit to an external power source providing a supply voltage, said power terminal being connected within said circuit to an element for supplying said supply voltage to said second common mode; and a ground terminal for connecting the source of said fifth MOS transistor to ground.

Claim 12

A circuit as claimed in claim 8, wherein when the first and second binary signals are different in logical level from each other, said second MOS transistor, said third MOS transistor and said fifth MOS transistor are turned on and said first MOS transistor and said fourth MOS transistor are turned off or said second MOS transistor, said third MOS transistor and said fifth MOS transistor are turned off and said first MOS transistor and said fourth MOS transistor are turned on and, when the first and second binary signals are equal in logical level to each other, said second MOS transistor and said fourth MOS transistor are turned on or said first MOS transistor and said third MOS transistor are turned on.

Claim 13

A circuit as claimed in claim 8, further comprising an auxiliary input terminal for connecting a third binary signal to the source of said first and second n-channel MOS transistors.

Claim 14

A circuit as claimed in claim 10, wherein when the first and second binary signals are equal in logic level to each other, the logic level on said output terminal is equal to the logic level of said third binary signal.

Claim 15

A circuit as claimed in claim 8, wherein said element for supplying said supply voltage comprises a p-channel MOS transistor.

Claim 16

A circuit as claimed in claim 8, wherein said element for supplying said supply voltage comprises a resistor.

Claim 17

A circuit as claimed in claim 8, further comprising a plurality of said comparing circuits cascaded in N consecutive stages with said output terminals and said auxiliary input terminals of said circuits adjacent to each other being connected to each other to form a circuit for comparing first and second N-bit binary signals, where N is a non-zero positive integer; wherein each bit of said first N-bit binary signal is supplied as said first binary signal to each of said N 1-bit comparing circuits on the gate electrode of said first n-channel MOS transistor, while each bit of second N-bit binary signal is supplied as said second binary signal to each of said N comparing circuits on the gate electrode of said third n-channel MOS transistor.