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Patent US4890305A successfully refreshed from Google Patents.
US4890305A
Expired / Lapsed
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Dual-tracking phase-locked loop
Assignee: Nortel Networks Ltd
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Filing: 1988-02-12
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Granted: 1989-12-26
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Expires: 2008-02-12
Abstract
Abstract A dual-tracking phase-locked loop circuit is provided for moving with minimum disruption from conventional PLL operation to processor-controlled tracking of another closely related clock. In addition to conventional PLL components the circuit comprises a processor-controlled up/down counter which may operate alternatively as a link in the loop or as providing the base-line frequency determining value at the time of transition from PLL to processor-controlled tracking operation, thereby ensuring none disruptive transition.
Inventors
- 👤 Paul A. DeVries
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:08
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/14; H03L7/146; H03L7/148; H03L7/085; H03L7/093; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
150 words
A dual-tracking phase-locked loop (DTPLL), comprising: phase detection means responsive to the phases of active and back-up clock signals; comparator means responsive to said phase detection means and to programmable counter means counting up or down in response to said comparator means; oscillator means responsive to said programmable counter means for providing said back-up clock signal; and said programmable counter means comprising a microprocessor for latching a digital value in an up/down counter in response to change in a master clock recovered from an incoming data stream, and a digital-to-analog (D/A) convertor for converting the latched value to an analog value for controlling the frequency of said oscillator means so that when the microprocessor senses said changes in said master clock and latches said digital value, it inhibits the up/down counter from counting and causes said phase detection means and said comparator means to cease to affect said oscillator means.
Claim 2
Dependent Claim
150 words
A dual-tracking phase-locked loop (DTPLL), comprising: phase detection means responsive to the phases of active and back-up clock signals; comparator means responsive to said phase detection means and to programmable counter means counting up or down in response to said comparator means; oscillator means responsive to said programmable counter means for providing said back-up clock signal; and said programmable counter means comprising a microprocessor for latching a digital value in an up/down counter in response to change in a master clock recovered from an incoming data stream, and a digital-to-analog (D/A) convertor for converting the latched value to an analog value for controlling the frequency of said oscillator means so that when the microprocessor senses said changes in said master clock and latches said digital value, it inhibits the up/down counter from counting and causes said phase detection means and said comparator means to cease to affect said oscillator means.
Claim 3
Dependent Claim
93 words
A dual-tracking phase-locked loop (DTPLL), comprising: a phase-locked loop (PLL) circuit wherein a clock determining voltage-controlled oscillator (VCO) is controlled by a digitally encoded value determined by a phase comparator in the PLL circuit comparing an active clock and said VCO, said digitally encoded value is stored in an up/down counter, and wherein the digitally encoded value ceases, at a predetermined time, to be determined by said phase comparator and is determined instead by a microprocessor means for controlling said up/down counter, whereby the VCO clock exhibits minimal disruption at said predetermined time.
Claim 4
Dependent Claim
93 words
A dual-tracking phase-locked loop (DTPLL), comprising: a phase-locked loop (PLL) circuit wherein a clock determining voltage-controlled oscillator (VCO) is controlled by a digitally encoded value determined by a phase comparator in the PLL circuit comparing an active clock and said VCO, said digitally encoded value is stored in an up/down counter, and wherein the digitally encoded value ceases, at a predetermined time, to be determined by said phase comparator and is determined instead by a microprocessor means for controlling said up/down counter, whereby the VCO clock exhibits minimal disruption at said predetermined time.
Claim 5
Dependent Claim
15 words
The DTPLL as defined in claim 2, said up/down counter being a programmable up/down counter.
Claim 6
Dependent Claim
28 words
The DTPLL as defined in claim 3, said progammable up/down counter being inserted in and out of said PLL by being enabled and disabled, respectively, by said microprocessor.
Claim 7
Dependent Claim
23 words
The DTPLL as defined in claim 4, said programmable up/down counter being enabled by said microprocessor when said DTPLL is in back-up mode.
Claim 8
Dependent Claim
33 words
The DTPLL as defined in claims 4 or 5, said programmable up/down counter being disabled at said predetermined time when said DTPLL is to provide the VCO clock under control of said microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-25 | 1993-06-26 | 1993-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-25 | 1997-06-26 | 1997-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-25 | 2001-06-26 | 2001-12-26 | $7700.00 | Window Closed / Lapsed |