Signed digit adder circuit

Claim 2

Apparatus for adding two signed digit addends, X and Y, each addend having a plurality of digits, each addend representable by logical sign portions, X s and Y s and logical magnitude portions, X m and Y m , comprising: first logic circuitry for generating a first logical output for each digit of the respective addends based on the signs of the respective addends; second logic circuitry to generate a first intermediate logical value for each digit of the respective addends from the sign and magnitude portions of the respective addends; third logic circuitry to generate a second intermediate logical value for each digit of the respective addends from the magnitudes of the respective addends; fourth logic circuitry for generating a second logical output from said first and second intermediate logical values and from a first logical output generated for a preceding pair of signed digit addends; fifth logic circuitry for generating a third intermediate logical value from said second intermediate logical value and from said first logical output generated for said preceding pair of signed digit addends; and sixth logic circuitry for generating a sum digit for each pair of associated position digits of said addends from said third intermediate logical value and a second logical output generated for a preceding pair of signed digital addends.

Claim 3

The apparatus of claim 1 wherein said second logic circuitry includes circuitry for calculating the logical equation Q=(NOT (X s )+NOT (Y s ))·X m for each said pair of associated position digits where Q represents said first intermediate logical value.

Claim 4

The apparatus of claim 2 wherein said third logic circuitry further includes circuitry for calculating the logical equation E=X m XOR Y m for each said pair of associated position digits where E represents said second intermediate logical value.

Claim 5

The apparatus of claim 3 wherein said fourth logic circuitry includes circuitry for calculating the logical equation U=E·NOT (R -1 )+NOT(Q)·NOT (E) for each said pair of associated position digits where Q represents said first intermediate logical value and R -1 represents a first logical output generated for a preceding pair of signed digit addends.

Claim 6

A circuit for adding two signed digit addends, X and Y, said signed digit addends having digits each representable by logical sign portions X s and Y s and logical magnitude portions X m and Y m , said circuit having a plurality of successively interconnected cells, each cell having inputs for receiving respective digits and for receiving outputs from the preceding cell, each cell comprising: circuitry for generating a first logical output based on the signs of the addends; circuitry for generating a first intermediate logical value based on the signs and magnitudes of the addends; circuitry for generating a second intermediate logical value based on the magnitudes of the addends; circuitry for generating a third intermediate logical value based on said second intermediate logical value and on a first logical output generated by a preceding cell, said circuitry for generating said third intermediate logical value being optimized to generate said third intermediate value in response to the availability of valid outputs from said circuitry for generating the second intermediate logical value; circuitry for generating a second logical output based on said first and second intermediate logical values and on said first logical output generated by said preceding cell; and circuitry for generating a sum digit representable by logical sign and magnitude portions, and based on said second logical output generated by the preceding cell and said third intermediate logical value.

Claim 7

A circuit for adding two signed digit addends, X and Y, said signed digit addends having digits each representable by logical sign portions X s and Y s and logical magnitude portions X m and Y m , said circuit having a plurality of successively interconnected cells, each cell having inputs for receiving respective digits and for receiving outputs from the preceding cell, each cell comprising: circuitry for generating a first logical output based on the signs of the addends; circuitry for generating a first intermediate logical value based on the signs and magnitudes of the addends; circuitry for generating a second intermediate logical value based on the magnitudes of the addends; circuitry for generating a third intermediate logical value based on said second intermediate logical value and on a first logical output generated by a preceding cell, said circuitry for generating said third intermediate logical value being optimized to generate said third intermediate value in response to the availability of valid outputs from said circuitry for generating the second intermediate logical value; circuitry for generating a second logical output based on said first and second intermediate logical values and on said first logical output generated by said preceding cell; and circuitry for generating a sum digit representable by logical sign and magnitude portions, and based on said second logical output generated by the preceding cell and said third intermediate logical value.

Claim 8

The adding circuit of claim 5 wherein said circuitry for generating said first logical output comprises circuitry for calculating the logical equation R =X s NOR Y s , where R represents the first logical output.

Claim 9

The adding circuit of claim 6 wherein said circuitry for calculating R comprises a NOR gate.

Claim 10

The adding circuit of claim 5 wherein said circuitry for generating said first logical intermediate value comprises circuitry for calculating the logical equation Q =(NOT (X s )+NOT (Y s ))·X m .

Claim 11

The adding circuit of claim 8 wherein said circuitry for calculating Q comprises: a first P-channel transistor having a gate driven by Y s , a source connected to a logical high voltage, and a drain connected to a first node; a second P-channel transistor having a gate driven by X s , a source connected to a logical high voltage, and a drain connected to said first node; a third P-channel transistor having a gate driven by an inverted X m , a source connected to said first node and a drain connected to a second node; a first N-channel transistor having a gate driven by X s , a source connected to said second node and a drain connected to a third node; a second N-channel transistor having a gate driven by Y s , a source connected to said third node and a drain connected to ground voltage; and a third N-channel transistor having a gate driven by an inverted X m , a source connected to said second node and a drain connected to ground voltage, the signal representing Q being present at such second node.

Claim 12

The adding circuit of claim 9 and further comprising an inverter attached to said second node for generating an inverted Q signal.

Claim 13

The adding circuit of claim 5 wherein said circuitry for generating said second logical intermediate value comprises circuitry for calculating the logical equation E =X m XOR Y m .

Claim 14

The adding circuit of claim 11 wherein said circuit for calculating E comprises: a transmission gate having a control gate connected to an inverted X m , a complementary control gate connected to X m , an input connected to Y m and an output connected to a first node; a first N-channel transistor having a gate driven by X m , a source connected to said first node and a drain connected to a second node; a second N-channel transistor having a gate driven by Y m , a source connected to said second node and a drain connected to ground voltage; and a P-channel transistor having a gate driven by Y m , a source connected to said first node and a drain connected to X m , the signal representing E being present at said first node.

Claim 15

The adding circuit of claim 12 wherein said circuit for calculating E further comprises an inverter attached to said first node for generating an inverted E signal.

Claim 16

The adding circuit of claim 5 wherein said circuitry for generating said second logical output comprises circuitry for calculating the logical equation U=E·NOT (R -1 )+NOT (E)·NOT (Q).

Claim 17

The adding circuit of claim 14 wherein said circuitry for calculating U comprises: a first transmission gate having a control gate connected to an inverted E signal, a complementary control gate connected to an E signal, an input connected to an inverted Q signal and an output connected to a node for sensing the second logical output; and a second transmission gate having a control gate connected to said E signal, a complementary control gate connected to said inverted E signal, an input connected to an inverted first logical output from said preceding cell, and an output connected to the node for sensing the second logical output.

Claim 18

The adding circuit of claim 5 wherein said circuitry for generating said third logical intermediate value comprises circuitry for calculating the logical equation T=E XOR NOT (R -1 ), where T represents said third logical intermediate value.

Claim 19

The adding circuit of claim 16 wherein said circuitry for calculating T comprises: a first transmission gate having a control input connected to said E signal, a complementary control gate connected to said inverted E signal, and input connected to said first logical output from said preceding cell and an output connected to a node for sensing a T signal; and a second transmission gate having a control gate connected to said inverted E signal, a complementary control gate connected to said E signal, an input connected to said inverted first logical output from said preceding cell, and an output connected to said first node, said T signal being present on said node for sensing the T signal.

Claim 20

The adding circuit of claim 17 wherein said circuitry to calculating T further comprises: a third transmission gate having a control gate driven by said E signal, a complementary control gate connected to said inverted E signal, an input connected to said inverted first logical output from said preceding cell, and an output connected to a node for sensing an inverted T signal; and a fourth transmission gate having a control gate connected to said inverted E signal, a complementary control gate connected to said E signal, an input connected to said first logical output from said preceding cell; and an output connected to said node for sensing the inverted T signal.

Claim 21

The adding circuit of claim 5, wherein said circuitry for generating said sum digit comprises circuitry for generating a first sum output representing the sign portion of the output digit and circuitry for calculating a second sum output representing the magnitude portion of the sum digit.

Claim 22

The adding circuit of claim 19 wherein said circuitry to generate said first sum output comprises circuitry to calculate the logical equation Z s =T·U -1 , where U -1 represents the second logical output from said preceding cell, and Z s represents the sign portion of the sum digit.

Claim 23

The adding circuit of claim 20 wherein said circuitry to calculate said second sum output comprises circuitry to calculate the logical expression Z m =NOT (T) XOR U -1 , where U -1 represents said second logical output from said preceding cell and Z m represents the magnitude portion of the sum digit.

Claim 24

The adding circuit of claim 21 wherein said circuitry to calculate the logical equation Z m =NOT(T) XOR U -1 comprises: a first transmission gate having an input connected to U -1 , a control gate driven by a NOT(T) signal, a complementary control gate driven by a T signal, and an output connected to a node for sensing an inverted Z m signal; a first N-channel transistor having a gate connected to U -1 , a source connected said node for sensing an inverted Z m signal, and a drain connected to a source of a second N-channel transistor, said second N-channel transistor having a gate driven by said T signal and a drain connected to ground; a first P-channel transistor having a gate driven by said U -1 signal, a drain connected to said node for sensing the inverted Z m signal, and a source connected to a drain of a second P-channel transistor having a gate driven by said NOT(T) signal and a source connected to a logical high voltage; and an inverter having its input connected to said node for sensing the inverted Z m signal; the Z m signal being present at the output of said inverter.

Claim 27

The method of claim 23 wherein said step of generating the first intermediate logical value comprises calculting the logical equation Q=(NOT (X s )+NOT (Y s ))·X m for each said pair of associated position digits where Q represents said first logical intermediate value.

Claim 28

The method of claim 24 wherein said step of generating the first intermediate logical value comprises calculating the logical equation E=X m XOR Y m for each said pair of associated position digits, where E represents said second intermediate logical value.

Claim 29

The method of claim 25 wherein said step of generating said third intermediate logical value comprises calculating the logical equation T=E XOR NOT (R -1 ) for each said pair of associated position digits, where R -1 represents the first logical output generated for said pair of digits from said preceding pair of addends, and T represents said third logical intermediate value for the digit position.