Patent US4890071A successfully refreshed from Google Patents.
US4890071A
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Signal generator utilizing a combined phase locked and frequency locked loop
Assignee: Agilent Technologies Inc
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Filing: 1988-10-26
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Granted: 1989-12-26
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Expires: 2008-10-26
Abstract
Abstract A programmable low noise frequency modulated signal source including a voltage controlled oscillator (VCO) having a frequency locked loop (FLL) constituting a first feedback path and a phase lock loop (PLL) constituting a second feedback path is provided. The PLL includes a VCO, a programmable fractional-N frequency division network and a phase detector for comparing the phase of the VCO output signal with the phase of a reference signal and for producing an error signal to controllably adjust the output frequency of the VCO. The FLL includes a delay line frequency discriminator, a loop amplifier and filter to provide a feedback signal to a frequency control terminal of the VCO. The frequency discriminator includes a first signal path having a frequency sensitive time delay network to provide a phase shift as a function of the VCO output signal frequency and a second signal path which includes a voltage controlled phase shifting network. The error signal derived from the PLL phase detector is coupled to an input terminal at the voltage controlled phase shifting network. The PLL error signal in combination with a bias signal adjusts the phase difference between the two frequency discriminator signal paths to set the operating point of the FLL phase detector such that the VCO output signal will have a desired frequency and minimum phase noise.
Inventors
- 👤 George S. Curtis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:01
CPC Classifications
H; H03; H03C; H03C3/00; H03C3/02; H03C3/09; H03C3/0908; H03C3/0975; H03C3/0916; H03C3/0925; H03C3/0941; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/10; H03L7/113; H03L7/16; H03L7/18; H03L7/183; H03L7/187; H03L7/189; H03L7/197; H03B; H03B2201/00; H03B2201/02; H03B2201/0208; H03C2200/00; H03C2200/0037; H03C2200/005; H03C2200/0079; H03C2200/0083; H03C3/10; H03C3/12; H03C3/22
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
552 words
A frequency synthesizer apparatus of the phase locked loop type comprising: controlled oscillator means having an output terminal and a frequency control terminal, said controlled oscillator means providing an output signal to said output terminal having a selectable frequency determined by the magnitude of a frequency control signal applied to said frequency control terminal; a first feedback path responsive to said output signal provided by said controlled oscillator means to said output terminal thereof for supplying a feedback signal to said frequency control terminal of said controlled oscillator means, said first feedback path including a frequency discriminator network including a first phase detector means having an output port and first and second input ports and first coupling means for coupling said output signal from said output terminal to said first and second input ports of said first phase detector means, time delay means having a time delay of Tau, said time delay means being connected to delay said output signal coupled t one of said first and second input ports, variable phase shift means having a phase shift control terminal, said variable phase shift means connected to shift the phase of the output signal coupled to one of said first and second input ports of said first phase detector, said first phase detector providing a first error signal to said output port thereof, the magnitude of said first error signal proportional to the difference in phase between the signals coupled to said first and second input ports of said first phase detector, said first error signal provided by said first phase detector coupled to said frequency control terminal of said controlled oscillator means; a second feedback path responsive to said output signal provided by said controlled oscillator means to said output terminal thereof for supplying a feedback signal to said frequency control terminal of said controlled oscillator means, said second feedback path including a second phase detector means having an output port and first and second input ports, said first input port of said second phase detector coupled to said output terminal of said controlled oscillator means for receiving a signal at a frequency dependent on the output frequency of said controlled oscillator means, said second input port of said second phase detector means for receiving a reference signal having a predetermined frequency, said second phase detector providing a second error signal to said output port thereof, the magnitude of said second error signal proportional to the difference in phase between the signals coupled to said second phase detector, second coupling means coupling said second error signal to said phase shift control terminal of said variable phase shift means for controlling the magnitude of the phase shift provided by said variable phase shift means; and controller means responsive to an applied frequency selection signal representative of a currently selected controlled oscillator means output frequency, said controller means including means for providing a bias signal to said variable phase shift means that allows said variable phase shift means to provide as value of phase shift that causes the absolute value of said first error signal provided to the output port of said first phase detector to be equal to a minimum value when the current output frequency of the controlled oscillator means is equal to said currently selected controlled oscillator means output frequency.
Claim 2
Dependent Claim
552 words
A frequency synthesizer apparatus of the phase locked loop type comprising: controlled oscillator means having an output terminal and a frequency control terminal, said controlled oscillator means providing an output signal to said output terminal having a selectable frequency determined by the magnitude of a frequency control signal applied to said frequency control terminal; a first feedback path responsive to said output signal provided by said controlled oscillator means to said output terminal thereof for supplying a feedback signal to said frequency control terminal of said controlled oscillator means, said first feedback path including a frequency discriminator network including a first phase detector means having an output port and first and second input ports and first coupling means for coupling said output signal from said output terminal to said first and second input ports of said first phase detector means, time delay means having a time delay of Tau, said time delay means being connected to delay said output signal coupled t one of said first and second input ports, variable phase shift means having a phase shift control terminal, said variable phase shift means connected to shift the phase of the output signal coupled to one of said first and second input ports of said first phase detector, said first phase detector providing a first error signal to said output port thereof, the magnitude of said first error signal proportional to the difference in phase between the signals coupled to said first and second input ports of said first phase detector, said first error signal provided by said first phase detector coupled to said frequency control terminal of said controlled oscillator means; a second feedback path responsive to said output signal provided by said controlled oscillator means to said output terminal thereof for supplying a feedback signal to said frequency control terminal of said controlled oscillator means, said second feedback path including a second phase detector means having an output port and first and second input ports, said first input port of said second phase detector coupled to said output terminal of said controlled oscillator means for receiving a signal at a frequency dependent on the output frequency of said controlled oscillator means, said second input port of said second phase detector means for receiving a reference signal having a predetermined frequency, said second phase detector providing a second error signal to said output port thereof, the magnitude of said second error signal proportional to the difference in phase between the signals coupled to said second phase detector, second coupling means coupling said second error signal to said phase shift control terminal of said variable phase shift means for controlling the magnitude of the phase shift provided by said variable phase shift means; and controller means responsive to an applied frequency selection signal representative of a currently selected controlled oscillator means output frequency, said controller means including means for providing a bias signal to said variable phase shift means that allows said variable phase shift means to provide as value of phase shift that causes the absolute value of said first error signal provided to the output port of said first phase detector to be equal to a minimum value when the current output frequency of the controlled oscillator means is equal to said currently selected controlled oscillator means output frequency.
Claim 3
Dependent Claim
75 words
The frequency synthesizer apparatus as in claim 1 further comprising switching means coupled to said second phase detector output port for selectively coupling said second error signal to said controlled oscillator means frequency control terminal and decoupling said second error signal from said phase shift control terminal of said variable phase shift means when the frequency of said controlled oscillator means output signal is changed from a first desired frequency to a second desired frequency.
Claim 4
Dependent Claim
61 words
The frequency synthesizer apparatus as in claim 1 further comprising frequency divider means coupled between said controlled oscillator means output port and said second phase detector first input port, said frequency divider means for providing a signal to said second phase detector having a frequency substantially equal to the frequency of said output signal divided by a selectable predetermined rational number.
Claim 5
Dependent Claim
36 words
The frequency synthesizer apparatus as in claim 3 wherein said controlled oscillator means comprises a YIG tuned oscillator including a tuning coil for receiving a pretune signal for tuning said YIG oscillator to a desired frequency.
Claim 6
Dependent Claim
17 words
The frequency synthesizer apparatus as in claim 1 wherein said minimum value is substantially equal to zero.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-25 | 1993-06-26 | 1993-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-25 | 1997-06-26 | 1997-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-25 | 2001-06-26 | 2001-12-26 | $7700.00 | Window Closed / Lapsed |