An integrated controlled FET switch

Claim 2

In a switch means designed as an integrated circuit comprising: a signal input connected to a first controllable switch in the form of a first FET which switches off completely only within a predetermined input voltage range and which, upon receiving a control signal connects through an input signal; a second controllable switch in the form of a second FET connected between the first FET and an output of the switch means, said second FET being controlled in synchronism with the first FET; and, a third FET, serving as a clamp FET, connected between the common node of said first and second FETs and a point of constant voltage, said third FET in the conductive state clamping the node between the first FET and the second FET at the constant voltage and being switched in time synchronism with the first FET and the second FET to a state opposite that of the first FET and the second FET; the improvement wherein: the first FET and the second FET are of the same conductivity type and the third FET is of the opposite conductivity type; the gate electrodes of all of the first, second and third FETs are driven by control signals of the same polarity; and the point of constant voltage is the negative pole of an operating voltage source for the switch means if the third FET is of the n-channel type, and is the positive pole of the operating voltage source if the third FET is of the p-channel type.

Claim 3

A switch means according to claim 1, wherein the input of the switch means is connected to an overvoltage protection circuit.

Claim 4

A switch means according to claim 1, wherein two parallel signal paths, each having a respective said first FET, a respective said second FET and a respective said third FET, are connected between the input and the output of the switch means; and wherein the respective first FET and the respective second FET are formed by p-channel FETs and the respective third FET by an n-channel FET in one of said two signal paths, and the respective first FET and the respective second FET are formed by n-channel FETs and the respective third FET by a p-channel FET in the other of said two signal paths.

Claim 5

A switch means according to claim 3, wherein: two control signal sources for producing respectively complementary control signals are provided: and the control electrodes of the respective first, second and third FETs of one of said two signal paths are connected to one of said control signals sources, and the control electrodes of the respective first, second and third FETs of the other of said two signal paths are connected to the other of said two control signal sources.

Claim 6

A switch means according to claim 2 wherein said overvoltage protection circuit includes: a pair of series connected diodes connected between the positive and negative poles of the operating voltage source, with the point of common connection of said pair of diodes being connected to said signal input of said switch means.

Claim 7

A switch means according to claim 1, wherein all FETs are formed by MOS FETs.

Claim 8

A switch means according to claim 3, wherein all FETs are formed by MOS FETs.

Claim 9

A multiplexer having a plurality of signal channels with a respective controlled switch means in the form of an integrated circuit in each channel and with an output node common to all channels, wherein each of said switch means comprises: first and second FETs of the same conductivity type connected in series between a signal input and said common output node; a third FET of a conductivity type opposite that of said first and second FETs, said third FET being connected between the common node of said first and second FETs and a point of reference potential corresponding to one of the poles of a source of operating voltage for said switch means, and clamping said node to said reference potential when said third FET is conductive, and said third FET being a p-channel FET when said reference potential is the positive operating voltage and being an n-channel FET when said reference potential is the negative operating voltage; and control signal means for synchronously applying control pulses of the same polarity to the control electrodes of each of said first, second and third FETs to switch said FETs between conductive and non-conductive states.

Claim 10

A multiplexer having a plurality of signal channels with a respective controlled switch means in the form of an integrated circuit in each channel and with an output node common to all channels, wherein each of said switch means comprises: first and second FETs of the same conductivity type connected in series between a signal input and said common output node; a third FET of a conductivity type opposite that of said first and second FETs, said third FET being connected between the common node of said first and second FETs and a point of reference potential corresponding to one of the poles of a source of operating voltage for said switch means, and clamping said node to said reference potential when said third FET is conductive, and said third FET being a p-channel FET when said reference potential is the positive operating voltage and being an n-channel FET when said reference potential is the negative operating voltage; and control signal means for synchronously applying control pulses of the same polarity to the control electrodes of each of said first, second and third FETs to switch said FETs between conductive and non-conductive states.

Claim 11

A multiplexer according to claim 8, wherein an analog-to-digital converter is connected to the common output node.

Claim 12

A multiplexer having a plurality of signal channels with a respectively controlled switch means in the form of an integrated circuit in each channel and with an output node common to all channels, wherein each of said switch means comprises: first and second FETs of the p-channel type connected in series between a signal input and said common output node; a third FET of the n-channel type connected between the common node of said first and second FETs and a point of a first potential corresponding to the negative pole of a source of operating voltage for said switch means, and clamping said node at said first potential when said third FET is conductive; fourth and fifth FETs of the n-channel type connected in series between said input and said common output node; a sixth FET of the p-channel type connected between the common node of said fourth and fifth FETs and a point of second potential corresponding to the positive pole of the source of operating voltage, and clamping said node of said fourth and fifth FETs at said second potential when said sixth FET is conductive; and control signal means for synchronously applying control pulses of one polarity to the control electrodes of each of said first, second and third FETs and control pulses of the opposite polarity to the control electrodes of each of said fourth, fifth and sixth FETs to switch said FETs between conductive and non-conductive states.

Claim 13

A multiplexer having a plurality of signal channels with a respectively controlled switch means in the form of an integrated circuit in each channel and with an output node common to all channels, wherein each of said switch means comprises: first and second FETs of the p-channel type connected in series between a signal input and said common output node; a third FET of the n-channel type connected between the common node of said first and second FETs and a point of a first potential corresponding to the negative pole of a source of operating voltage for said switch means, and clamping said node at said first potential when said third FET is conductive; fourth and fifth FETs of the n-channel type connected in series between said input and said common output node; a sixth FET of the p-channel type connected between the common node of said fourth and fifth FETs and a point of second potential corresponding to the positive pole of the source of operating voltage, and clamping said node of said fourth and fifth FETs at said second potential when said sixth FET is conductive; and control signal means for synchronously applying control pulses of one polarity to the control electrodes of each of said first, second and third FETs and control pulses of the opposite polarity to the control electrodes of each of said fourth, fifth and sixth FETs to switch said FETs between conductive and non-conductive states.

Claim 14

A multiplexer according to claim 10, wherein an analog-to-digital converter is connected to the common output node.

Claim 15

A multiplexer having a plurality of channels with a respective controlled switch means in the form of an integrated circuit in each channel and with an output node common to all channels, wherein each of said switch means comprises: first, second and third pairs of parallelly connected complementary FETs connected sequentially in series between a signal input and said common output node; a first clamp FET connected between the common node of said first and second pairs of parallelly connected complementary transistors and a point of first potential corresponding to one of the positive and negative poles of an operating voltage source for said switch means, said first clamp FET clamping said node of said first and second pairs to said first potential when in a conductive state; a second clamp FET connected between the common node of said second and third pairs of parallelly connected complementary FETs and a point of second potential corresponding to the other of said positive and negative poles of the operating voltage source, said second clamp FET clamping said node of said second and third pairs to said second potential when in a conductive state; the one of said first and second clamp FETs connected to said positive pole being a p-channel FET and the other of said first and second clamp FETs being an n-channel FET; and control signal means connected to the gate electrodes of all of said FETs for synchronously switching said FETs of said pairs between conductive and non-conductive states, and said first and second clamp FETs between non-conductive and conductive states, respectively

Claim 16

A multiplexer having a plurality of channels with a respective controlled switch means in the form of an integrated circuit in each channel and with an output node common to all channels, wherein each of said switch means comprises: first, second and third pairs of parallelly connected complementary FETs connected sequentially in series between a signal input and said common output node; a first clamp FET connected between the common node of said first and second pairs of parallelly connected complementary transistors and a point of first potential corresponding to one of the positive and negative poles of an operating voltage source for said switch means, said first clamp FET clamping said node of said first and second pairs to said first potential when in a conductive state; a second clamp FET connected between the common node of said second and third pairs of parallelly connected complementary FETs and a point of second potential corresponding to the other of said positive and negative poles of the operating voltage source, said second clamp FET clamping said node of said second and third pairs to said second potential when in a conductive state; the one of said first and second clamp FETs connected to said positive pole being a p-channel FET and the other of said first and second clamp FETs being an n-channel FET; and control signal means connected to the gate electrodes of all of said FETs for synchronously switching said FETs of said pairs between conductive and non-conductive states, and said first and second clamp FETs between non-conductive and conductive states, respectively

Claim 17

A multiplexer according to claim 12, wherein an analog-to-digital converter is connected to the common output node.

Claim 18

A switch means designed as an integrated circuit for switching a signal within a predetermined input voltage range comprising: a signal input and a signal output; first, second and third pairs of parallelly connected complementary FETs connected sequentially in series between said signal input and said signal output; a first clamp FET connected between the common node of said first and second pairs of parallelly connected complementary transistors and a first potential corresponding to one of the positive and negative ends of said predetermined input voltage range, said first clamp FET clamping said node of said first and second pairs to said first potential when in a conductive state; a second clamp FET connected between the common node of said second and third pairs of parallelly connected complementary FETs and a second potential corresponding to the other of said positive and negative ends of said predetermined input voltage range, said second clamp FET clamping said node of said second and third pairs to said second potential when in a conductive state; the one of said first and second clamp FETs connected to the potential corresponding to said positive end of said input voltage range being a p-channel FET and the other of said first and second clamp FETs being an n-channel FET; and control signals means connected to the gate electrodes of all of said FETs for synchronously switching said FETs of said pairs between conductive and non-conductive states, and said first and second clamp FETs between non-conductive and conductive states, respectively.

Claim 19

A switch means designed as an integrated circuit for switching a signal within a predetermined input voltage range comprising: a signal input and a signal output; first, second and third pairs of parallelly connected complementary FETs connected sequentially in series between said signal input and said signal output; a first clamp FET connected between the common node of said first and second pairs of parallelly connected complementary transistors and a first potential corresponding to one of the positive and negative ends of said predetermined input voltage range, said first clamp FET clamping said node of said first and second pairs to said first potential when in a conductive state; a second clamp FET connected between the common node of said second and third pairs of parallelly connected complementary FETs and a second potential corresponding to the other of said positive and negative ends of said predetermined input voltage range, said second clamp FET clamping said node of said second and third pairs to said second potential when in a conductive state; the one of said first and second clamp FETs connected to the potential corresponding to said positive end of said input voltage range being a p-channel FET and the other of said first and second clamp FETs being an n-channel FET; and control signals means connected to the gate electrodes of all of said FETs for synchronously switching said FETs of said pairs between conductive and non-conductive states, and said first and second clamp FETs between non-conductive and conductive states, respectively.

Claim 20

A switch means according to claim 14, wherein: said control signal means comprises two control signal sources for producing respectively complementary control signals; the control electrodes of the FETs of one conductivity type of each of said first, second and third pairs are all connected to one of said two control signal sources, and the control electrodes of the FETs of the other conductivity type of each of said first, second and third pairs are all connected to the other of said two control signal sources; and the control electrode of each said first and second clamp FETs is connected to a respectively different one of said two control signal sources.

Claim 21

A switch means according to claim 14, wherein all FETs are formed by MOS FETs.

Claim 22

A switch means according to claim 14 wherein said first potential corresponds to said positive end of said predetermined input voltage range.

Claim 23

A switch means according to claim 17 wherein said first and second potentials correspond to the respective poles of an operating voltage source for said integrated circuit.

Claim 24

A controllable integrated switching circuit for switching an input signal on and off comprising: first and second FETs of the same conductivity type connected in series between a signal input and a signal output; a third FET of a conductivity type opposite that of said first and second FETs, with said third FET being connected between the common node of said first and second FETs and a point of reference potential corresponding to one of the poles of a source of operating voltage for said circuit, and clamping said node to said reference potential when said third FET is conductive, and with said third FET being a p-channel FET when said reference potential is the positive operating voltage and being an n-channel FET when said reference potential is the negative operating voltage; and control signal means for synchronously applying control pulses of the same polarity to the control electrodes of each of said first, second and third FETs to switch said FETs between conductive and non-conductive states.

Claim 25

A controllable integrated switching circuit for switching an input signal on and off comprising: first and second FETs of the same conductivity type connected in series between a signal input and a signal output; a third FET of a conductivity type opposite that of said first and second FETs, with said third FET being connected between the common node of said first and second FETs and a point of reference potential corresponding to one of the poles of a source of operating voltage for said circuit, and clamping said node to said reference potential when said third FET is conductive, and with said third FET being a p-channel FET when said reference potential is the positive operating voltage and being an n-channel FET when said reference potential is the negative operating voltage; and control signal means for synchronously applying control pulses of the same polarity to the control electrodes of each of said first, second and third FETs to switch said FETs between conductive and non-conductive states.

Claim 26

A controllable integrated switch circuit according to claim 19 further comprising an overvoltage protection circuit means, including a protective diode network, connected to said signal input for protecting said switching circuit from excess voltages.