Algebraic coder-decoder for Reed Solomon and BCH block codes, applicable to telecommunications

Claim 1

An algebraic Reed Solomon and BCH block code coder-decoder comprising: a processor means; a clock generator coupled to said processor means; an arithmetic operator means coupled to said processor means; a Galois operator coupled to said processor means for processing values in Galois bodies having a computation means having two inputs; two independent addressable memories of matched capacities coupled to the inputs of said computation means; an indirect memory access means operatively associated with said Galois operator for controlling access to said two memories; an operator circuit control means organized on three levels, the first level being for the selection of data sources, the second for the storage of three operands X, Y and Z; and the third for computation of X+(YxZ) from said stored operands and for executing block code coding and decoding algorithms; a control and interface circuit contained as part of said processor means and having I/O access and connected to a data bus for controlling access to said I/O and for executing a sequence of operations including initialization of said access and polynomial computations; wherein said two independent memories coupled to computation means are used as FIFO memories for said control and interface circuit on a cycle stealing arrangement.