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EP0169908A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method and circuit for decoding error coded data

Assignee: Sony Corp
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Filing: 1985-01-18
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Granted: —
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Expires: 2005-01-18
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Abstract

Abstract A microprocessor is employed to carry out multiplication or division in relation to two unknowns on finite fields. To perform multiplication or division in relation to two unknowns α i and a, the unkown a represented by a vector is stored in an accumulator. The contents of the accumulator and a primitive polynomial represented by a vector are added together by an adder (mod. 2). The result of the addition is then stored in an accumulator. The bit shift of the accumulator and the operation of the adder are controlled according to a program. When multiplication or division in relation to two unknowns α i and α j is carried out, the unknowns are converted into exponents i and j and subjected to exponential addition and subtraction, and the result of the exponential calculation is converted into a vectorial representation.

Inventors

  • 👤 Katsuya Sony Corporation Hori
  • 👤 Tsuneo Sony Corporation Furuya

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 16:12
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/72; G06F7/724; G06F7/726; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1809; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; G11B27/3063; H; H03; H03M; H03M13/00; H03M13/03; H03M13/033; H03M13/05; H03M13/13; H03M13/15; G06F1/00; G06F1/02; G06F1/03; G06F1/0307

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 96 words
A circuit for operating finite fields which performs a multiplication or a division in relation to arbitrary elements a i and a over a finite field (where, a is a root of a primitive polynomial of said finite field), comprising: an accumulator for storing said arbitrary element a i ; an adder for performing an addition of (mod. 2) in relation to the contents of said accumulator and said primitive polynomial; represented by a vector; a control section for controlling the bit-shift in said accumulator and the operation of said adder in accordance with a program.
Claim 2
Dependent Claim 96 words
A circuit for operating finite fields which performs a multiplication or a division in relation to arbitrary elements a i and a over a finite field (where, a is a root of a primitive polynomial of said finite field), comprising: an accumulator for storing said arbitrary element a i ; an adder for performing an addition of (mod. 2) in relation to the contents of said accumulator and said primitive polynomial; represented by a vector; a control section for controlling the bit-shift in said accumulator and the operation of said adder in accordance with a program.
Claim 3
Dependent Claim 115 words
A circuit for operating finite fields which performs a multiplication or a division in relation to two elements α i and α j over a finite field (where, a is a root of a primitive polynomial of said finite field), comprising: a first table for generating the exponents from the elements over said finite field; a second table for generating the elements over said finite field from said exponents; a binary arithmetic operating unit for performing an addition or a subtraction of said exponents; and a control section for controlling data conversions which are performed by said first and second tables and an operation of said binary arithmetic operating unit in accordance with a program.
Claim 4
Dependent Claim 115 words
A circuit for operating finite fields which performs a multiplication or a division in relation to two elements α i and α j over a finite field (where, a is a root of a primitive polynomial of said finite field), comprising: a first table for generating the exponents from the elements over said finite field; a second table for generating the elements over said finite field from said exponents; a binary arithmetic operating unit for performing an addition or a subtraction of said exponents; and a control section for controlling data conversions which are performed by said first and second tables and an operation of said binary arithmetic operating unit in accordance with a program.

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