Patent US4888765A successfully refreshed from Google Patents.
US4888765A
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Digital loop carrier system having programmable timeslot and bandwidth allocation circuit
Assignee: Nokia of America Corp
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Filing: 1988-08-22
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Granted: 1989-12-19
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Expires: 2008-08-22
Abstract
Abstract A system for allocating a plurality of channel units to a transmission line having a plurality of timeslots including bandwidth and multiple time slot allocation. The system has a counter and a parallel to serial register for providing a channel address via an address signal corresponding to a predetermined one of the plurality of timeslots to each of the channel units. A processor is provided for assigning an assigned address to each channel unit of the plurality of channel units, such channel unit being assigned to a different selected timeslot of the plurality of timeslots. Each of the channel units has a comparator for comparing the channel address in the address signal to the assigned address, the channel unit upon having a correspondence between the channel address and the assigned address, transmitting and receiving on the transmission line. A bus connects the plurality of channel units to the means for addressing. An active channel unit can retain control of the transmission line for bandwidth and multiple time slot allocation.
Inventors
- 👤 Harry J. Dyke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:07
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/24
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
221 words
A system for selectively allocating individual ones of a plurality of channel units to transmit and receive data on a transmission line during a plurality of timeslots of a pulse code modulation serial signal transmitted on a time division multiplexing basis, comprising: means for providing a plurality of timeslot binary addresses respectively corresponding to said plurality of timeslots, each of said timeslot binary addresses being provided the timeslot corresponding thereto on a plurality of timeslot address output lines of a register; a bus for connecting all said plurality of channel units to said timeslot binary address providing means; means for assigning a plurality of channel unit binary addresses to said plurality of channel units which respectively correspond to said plurality of timeslots and to the plurality of timeslot binary addresses corresponding thereto, said channel unit binary addresses being assigned on a relatively permanent basis on a plurality of channel unit binary address output lines of another register; and means associated with each of said channel units including means for comparing each of said timeslot binary addresses with said channel unit binary address assigned thereto, said comparing means being responsive to a correspondence between said timeslot binary address and said assigned channel unit binary address by said comparing means to enable transmitting and receiving by said channel unit on said transmission line.
Claim 2
Independent Claim
221 words
A system for selectively allocating individual ones of a plurality of channel units to transmit and receive data on a transmission line during a plurality of timeslots of a pulse code modulation serial signal transmitted on a time division multiplexing basis, comprising: means for providing a plurality of timeslot binary addresses respectively corresponding to said plurality of timeslots, each of said timeslot binary addresses being provided the timeslot corresponding thereto on a plurality of timeslot address output lines of a register; a bus for connecting all said plurality of channel units to said timeslot binary address providing means; means for assigning a plurality of channel unit binary addresses to said plurality of channel units which respectively correspond to said plurality of timeslots and to the plurality of timeslot binary addresses corresponding thereto, said channel unit binary addresses being assigned on a relatively permanent basis on a plurality of channel unit binary address output lines of another register; and means associated with each of said channel units including means for comparing each of said timeslot binary addresses with said channel unit binary address assigned thereto, said comparing means being responsive to a correspondence between said timeslot binary address and said assigned channel unit binary address by said comparing means to enable transmitting and receiving by said channel unit on said transmission line.
Claim 3
Dependent Claim
55 words
The system according to claim 1 wherein said channel unit binary address assigning means includes means for selectively causing one of said channel units to transmit and receive data on said transmission line during a timeslot of another channel unit of lower priority in addition to the timeslot corresponding to its channel unit binary address.
Claim 4
Dependent Claim
29 words
The system according to claim 2 wherein said selective causing means causes a channel unit to transmit and receive during at least two consecutive timeslots on said transmission line.
Claim 5
Dependent Claim
50 words
The system according to claim 3 wherein at least one of said channel units includes means for controlling the timeslot binary addresses providing means during the timeslot corresponding to its assigned channel unit binary address to enable it to continue to transmit and receive during at least one following timeslot.
Claim 6
Dependent Claim
57 words
The system according to claim 1 wherein said means for providing a timeslot binary address has means for counting a multiplex channel clock signal and a parallel to serial register, said parallel to serial register responsive to said counting means for providing said timeslot binary addresses in serial form to all said channel units on said bus.
Claim 7
Dependent Claim
21 words
The system according to claim 5 wherein said count is periodically incremented and synchronized to said timeslots on said transmission line.
Claim 8
Dependent Claim
55 words
The system according to claim 5 including means for controlling the loading of the clock signal into said parallel to serial register for causing said parallel to serial register to provide the same address corresponding to a timeslot as was provided for a previous timeslot to enable multiple timeslot assignment to a selected channel unit.
Claim 9
Dependent Claim
50 words
The system according to claim 7 including means for latching said parallel to serial register and wherein said means for providing a timeslot binary address has a transmit serial control register responsive to a signal TSIG from a channel unit to cause said loading controlling means to operate said register.
Claim 10
Dependent Claim
80 words
The system according to claim 1 wherein each of said channel units has a parallel to serial register for receiving at least said timeslot binary address on said bus, a timeslot assigned register for receiving said assigned channel unit binary address from said channel unit binary address assigning means, and means connected to respective outputs of said parallel to serial register and to said time slot assigned register for comparing the timeslot binary address with the channel unit binary address.
Claim 11
Dependent Claim
36 words
The system according to claim 1 wherein said bus has at least an address line, a clock line and a strobe line connected between said timeslot binary address providing means and each of said channel units.
Claim 12
Dependent Claim
24 words
The system according to claim 9 wherein said bus has a plurality of lines connecting each of said channel units to said transmission line.
Claim 13
Dependent Claim
24 words
The system according to claim 8 wherein said bus has a line connecting each of said channel units to said transmit serial control register.
Claim 14
Independent Claim
118 words
A system for system actively allocating a plurality of channel units to transmit and receive on a transmission line during a plurality of timeslots of a pulse code modulated, serial transmission formatted signal on a time multiplexing basis, comprising: means for selecting one of said plurality of channel units; means for enabling said selected channel unit to transmit and receive on said transmission line during one of said plurality of timeslots, said selected channel unit transmitting and receiving during said one timeslot; and said selected channel unit having means associated therewith for controlling said selecting means to retain a connection with said transmission line to transmit and receive during at least an additional timeslot following said one timeslot.
Claim 15
Independent Claim
118 words
A system for system actively allocating a plurality of channel units to transmit and receive on a transmission line during a plurality of timeslots of a pulse code modulated, serial transmission formatted signal on a time multiplexing basis, comprising: means for selecting one of said plurality of channel units; means for enabling said selected channel unit to transmit and receive on said transmission line during one of said plurality of timeslots, said selected channel unit transmitting and receiving during said one timeslot; and said selected channel unit having means associated therewith for controlling said selecting means to retain a connection with said transmission line to transmit and receive during at least an additional timeslot following said one timeslot.
Claim 16
Dependent Claim
36 words
The system according to claim 13 wherein said controlling means includes means for controlling the selecting means to enable the selected channel unit to transmit and receiving in a plurality of timeslots following said one timeslot.
Claim 17
Dependent Claim
42 words
The system according to claim 13 wherein said controlling means has means for relinquishing control of the selecting means to enable another channel unit of said plurality of channel units to transmit and receive on the transmission line during a subsequent timeslot.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-18 | 1993-06-19 | 1993-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-18 | 1997-06-19 | 1997-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-18 | 2001-06-19 | 2001-12-19 | $7700.00 | Window Closed / Lapsed |