US4888628A
Expired / Lapsed
US
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Dynamic memory in integrated circuit form
Assignee: Eurotechnique SA
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Filing: 1986-02-10
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Granted: 1989-12-19
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Expires: 2006-02-10
Abstract
Abstract In a dynamic memory for capacitive data storage, enhanced storage performances are achieved by increasing the value of the storage capacitance. A junction capacitor is formed between the source region and the well region in which the memory cells are formed, the junction capacitor being associated with a conventional capacitor. By judiciously and heavily doping the wells, the junction capacitances are appreciably increased. The heavy-doping operation is performed by backward implantation of the wells at very high energy in order to place the concentration peak of the wells at the depth of the base of the thick oxides which form separations between memory cells.
Inventors
- 👤 Albert Bergemont
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 01:47
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
126 words
A dynamic memory in integrated circuit form for capacitive data storage of the type in which each memory cell comprises an MOS transistor having a given first channel polarity and formed in a well having a reverse second polarity in a semi-conductor substrate of the first polarity, said well having a high implant energy retrograde, wherein said memory comprises means for increasing the junction capacitance of the source-well junction of the transistor, and wherein the means for increasing the junction capacitance comprise unequally doped well regions in which the doping peak is located on the one hand in the immediate vicinity of the drain-source regions of the transistor and on the other hand directly beneath thick oxide regions which separate adjacent memory cells in the memory.
Claim 2
Dependent Claim
126 words
A dynamic memory in integrated circuit form for capacitive data storage of the type in which each memory cell comprises an MOS transistor having a given first channel polarity and formed in a well having a reverse second polarity in a semi-conductor substrate of the first polarity, said well having a high implant energy retrograde, wherein said memory comprises means for increasing the junction capacitance of the source-well junction of the transistor, and wherein the means for increasing the junction capacitance comprise unequally doped well regions in which the doping peak is located on the one hand in the immediate vicinity of the drain-source regions of the transistor and on the other hand directly beneath thick oxide regions which separate adjacent memory cells in the memory.
Claim 3
Dependent Claim
29 words
A memory according to claim 1, wherein the doping peaks correspond to an impurity concentration of the order of 10 17 to 10 18 atoms per cm 3 .
Claim 4
Dependent Claim
19 words
A memory according to claim 1, wherein said memory comprises means for adjusting the value of the junction capacitance.
Claim 5
Dependent Claim
20 words
A memory according to claim 1, wherein said memory comprises means for increasing the surface area of the source-well junction.
Claim 6
Dependent Claim
31 words
A memory according to claim 1, wherein said memory comprises means for reducing capacitances of transfer lines which transmit data between memory cells and circuits that are external to the memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-18 | 1993-06-19 | 1993-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-18 | 1997-06-19 | 1997-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-18 | 2001-06-19 | 2001-12-19 | $7700.00 | Window Closed / Lapsed |