Constant current biased common gate differential sense amplifier

Claim 2

A FET sense amplifier for sensing a pair of data lines coupled to a memory comprising: a first and second common gate transistors of a first conductivity type, wherein an input terminal of said first transistor is coupled to a first of said data lines and an input terminal of said second transistor is coupled to a second of said pair of data lines; a third and fourth common gate transistors of said first conductivity type, wherein an input terminal of said third transistor is coupled to said first date line and a input terminal of said fourth transistor is coupled to said second data line; said first, second, third and fourth common gate transistors having their gates coupled together to a first reference voltage source; a fifth and sixth transistors having their gates coupled to a second reference voltage source, wherein one terminal of said fifth transistor is coupled to said first data line and said input terminals of said first and third transistors; and one terminal of said sixth transistor is coupled to said second data line and said input terminals of said second and fourth transistors; a first active load coupled to output terminals of said first and second transistors; a second active load coupled to output terminals of said third and fourth transistors; said first reference voltage source biasing gates of said fifth and sixth transistors to operate in a saturation region; said second reference voltage source biasing said first, second, third and fourth transistors, wherein these four said common gate transistors conduct to bias said one terminals of said fifth and sixth transistors such that conduction of said four common gate transistors also biases said fifth and sixth transistors to operate in said saturation region; said fifth and sixth transistors operating in said saturation region to function as a current source to said common gate transistors, wherein voltage changes on said data lines are compensated by said current source transistors to prevent signal loss; whereby an improved sense amplifier is achieved.

Claim 3

The sense amplifier of claim 1 wherein said first active load converts differential inputs to said first and second transistors to a first single-ended output; and said second active load converts differential inputs to said third and fourth transistors to a second single-ended output; said first and second single-ended outputs providing a balanced differential output representative of signals present on said first and second data lines.

Claim 4

The sense amplifier of claim 2 further including a first driver stage coupled to said first active load and a second driver stage coupled to said second active load wherein each said driver stage for respectively amplifying said single-ended outputs of said active loads and providing an amplified balanced differential output representative of signals present on said data lines.

Claim 5

The sense amplifier of claim 3 wherein said first and second active loads are comprised of transistors having a second conductivity type.

Claim 6

The sense amplifier of claim 4 wherein said first, second, third and fourth common gate transistors are comprised of n-channel devices, and said first and said second active loads are comprised of p-channel transistors.

Claim 7

The sense amplifier of claim 5 wherein said fifth and sixth transistors are comprised of n-channel devices.

Claim 8

The sense amplifier of claim 6 wherein each of said first and second active loads further includes transistors disposed to function as a current mirror for providing said conversion of differential inputs to said single-ended output.

Claim 9

A FET sense amplifier for sensing a pair of data lines coupled to a memory comprising: a first and second common gate n-channel transistors, wherein source of said first transistor is coupled to a first of said pair of data lines and source of said second transistor is coupled to a second of said pair of data lines; a third and fourth common gate n-channel transistors, wherein source of said third transistor is coupled to said first data line and source of said fourth transistor is coupled to said second data line; said first, second, third and fourth transistors having their gates coupled together to a first reference voltage source; a fifth and sixth n-channel transistors having their gates coupled to a second reference voltage source, wherein drain of said fifth transistor is coupled to said first data line and source of said first and third transistors; drain of said sixth transistor is coupled to said second data line and sources of said second and fourth transistors; gates of said fifth and sixth transistors are coupled to a second reference voltage source; and sources of said fifth and sixth transistors coupled to a return of a voltage supply source; a first active load coupled to drains of said first and second transistors; a second active load coupled to drains of said third and fourth transistors; said first reference voltage source biasing gates of said fifth and sixth transistors to operate in a saturation region; said second reference voltage source biasing said first, second, third and fourth transistors, wherein these four said common-gate transistors conduct to bias drains of said fifth and sixth transistors, such that conduction of said four common-gate transistors also bias said fifth and sixth transistors to operate in said saturation region; said fifth and sixth transistors operating in said saturation region to function as a current source to said common gate transistors, wherein voltage changes on said data lines are compensated by said current source transistors to prevent signal loss; whereby an improved sense amplifier is realized.

Claim 10

A FET sense amplifier for sensing a pair of data lines coupled to a memory comprising: a first and second common gate n-channel transistors, wherein source of said first transistor is coupled to a first of said pair of data lines and source of said second transistor is coupled to a second of said pair of data lines; a third and fourth common gate n-channel transistors, wherein source of said third transistor is coupled to said first data line and source of said fourth transistor is coupled to said second data line; said first, second, third and fourth transistors having their gates coupled together to a first reference voltage source; a fifth and sixth n-channel transistors having their gates coupled to a second reference voltage source, wherein drain of said fifth transistor is coupled to said first data line and source of said first and third transistors; drain of said sixth transistor is coupled to said second data line and sources of said second and fourth transistors; gates of said fifth and sixth transistors are coupled to a second reference voltage source; and sources of said fifth and sixth transistors coupled to a return of a voltage supply source; a first active load coupled to drains of said first and second transistors; a second active load coupled to drains of said third and fourth transistors; said first reference voltage source biasing gates of said fifth and sixth transistors to operate in a saturation region; said second reference voltage source biasing said first, second, third and fourth transistors, wherein these four said common-gate transistors conduct to bias drains of said fifth and sixth transistors, such that conduction of said four common-gate transistors also bias said fifth and sixth transistors to operate in said saturation region; said fifth and sixth transistors operating in said saturation region to function as a current source to said common gate transistors, wherein voltage changes on said data lines are compensated by said current source transistors to prevent signal loss; whereby an improved sense amplifier is realized.

Claim 11

The sense amplifier of claim 8 wherein said first active load is comprised of a plurality of p-channel transistors and said second active load is also comprised of a plurality of p-channel transistors.

Claim 12

The sense amplifier of claim 9 wherein said first active load is coupled between drains of said first and second transistors and said supply voltage; and said second active load is coupled between drains of said third and fourth transistors and said supply voltage.

Claim 13

The sense amplifier of claim 10 wherein said first active load converts differential inputs to said first and second transistor to a first single-ended output, and said second active load converts differential inputs to said third and fourth transistors to a second single-ended output, wherein said first and second single-ended outputs provide a balanced differential output from said sense amplifier.

Claim 14

The sense amplifier of claim 11 further including a first and second driver, wherein said first driver is coupled to said first active load for providing a first amplified output of said first single-ended output, and said second driver is coupled to said second active load for providing a second amplified output of said second single-ended output, such that said first and second amplified outputs provide an amplified balanced differential output from said sense amplifier.

Claim 15

The sense amplifier of claim 12 wherein each of said first and second active loads further includes a current mirror to provide said conversion.

Claim 16

The sense amplifier of claim 13 wherein said first active load is comprised of seventh, eighth, ninth and tenth transistors, wherein said seventh and tenth transistors are coupled between drain of said first transistor and said supply voltage, said eighth and ninth transistors coupled between drain of said second transistor and supply voltage, and said seventh and eighth transistors operating as said current mirror; said second active load is comprised of eleventh, twelfth, thirteenth and fourteenth transistors, said eleventh and thirteenth transistors are coupled between drain of said third transistor and said supply voltage, said twelfth and fourteenth transistors are coupled between said fourth transistor and said supply voltage, and said eleventh and twelfth transistors operating as said current mirror.

Claim 17

The sense amplifier of claim 14 wherein gates of said ninth, tenth, thirteenth and fourteenth transistors are coupled together to a sense enable signal such that said first and second active loads are activated by said sense enable signal.

Claim 18

The sense amplifier of claim 15 wherein said first single-ended output is derived from drain of said first transistor and said second single-ended output is derived from drain of said fourth transistor.

Claim 19

The sense amplifier of claim 16 wherein said first and second voltage sources have a voltage potential of a value between Vcc and its return.

Claim 20

The sense amplifier of claim 17 wherein said amplified balanced differential output is centered approximately at one-half of said supply voltage.

Claim 21

The sense amplifier of claim 18 wherein said first and second drivers are precharged prior to amplifying said first and second single-ended outputs.

Claim 22

The sense amplifier of claim 19 wherein said plurality of said transistors of said first and second active loads are p-channel devices.