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Patent US4887267A successfully refreshed from Google Patents.
US4887267A
Expired / Lapsed
US
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Logic integrated circuit capable of simplifying a test
Assignee: Toshiba Corp
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Filing: 1987-12-28
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Granted: 1989-12-12
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Expires: 2007-12-28
Abstract
Abstract A logic integrated circuit includes a FIFO type memory circuit provided for testing. A logic value at each test node is stored in the memory circuits during a write-in enable period set by a control signal from a flip-flop or an externally supplied control signal, and the memory data is read out from the memory circuits, to trace the output states of internal bus, register, multiplier, and the like.
Inventors
- 👤 Akira Kanuma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 03:15
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318505
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
204 words
A logic integrated circuit comprising: a tested circuit to be inspected; a plurality of memory means of a FIFO memory type each of which have input terminals connected to respective test nodes of said tested circuit, for storing logical values from corresponding, respective test nodes, in response to commands executed by said tested circuit; and control means for controlling storage of the logical values in each of said plurality of memory means and read-out of the stored logical values from each of said plurality of memory means, said control means including decoder means, connected to said plurality of memory means, for selecting one of said plurality of memory means to read-out stored logical values from said one of said plurality of memory means and flip-flop means, connected to said plurality of memory means, for specifying a period during which corresponding logical values are stored in said respective memory means, and said control means successively storing the logical values at corresponding test nodes of said tested circuit in said memory means each time a write-in condition is satisfied during a period specified by said flip-flop means and for reading out data, after the end of write-in, from said memory means selected by said decoder means.
Claim 2
Dependent Claim
204 words
A logic integrated circuit comprising: a tested circuit to be inspected; a plurality of memory means of a FIFO memory type each of which have input terminals connected to respective test nodes of said tested circuit, for storing logical values from corresponding, respective test nodes, in response to commands executed by said tested circuit; and control means for controlling storage of the logical values in each of said plurality of memory means and read-out of the stored logical values from each of said plurality of memory means, said control means including decoder means, connected to said plurality of memory means, for selecting one of said plurality of memory means to read-out stored logical values from said one of said plurality of memory means and flip-flop means, connected to said plurality of memory means, for specifying a period during which corresponding logical values are stored in said respective memory means, and said control means successively storing the logical values at corresponding test nodes of said tested circuit in said memory means each time a write-in condition is satisfied during a period specified by said flip-flop means and for reading out data, after the end of write-in, from said memory means selected by said decoder means.
Claim 3
Dependent Claim
16 words
A logic integrated circuit according to claim 1, wherein said memory means comprises a shift register.
Claim 4
Dependent Claim
15 words
A logic integrated circuit according to claim 1, wherein said memory means comprises a RAM.
Claim 5
Dependent Claim
20 words
A logic integrated circuit according to claim 1, wherein said memory means comprises a serial input/parallel output type memory circuit.
Claim 6
Dependent Claim
26 words
A logic integrated circuit according to claim 1, wherein said flip-flop means is selectively set and reset in response to an externally supplied control input signal.
Claim 7
Dependent Claim
169 words
A logic integrated circuit comprising: a tested circuit to be inspected; a node selection means connected to test nodes of said tested circuit, for selecting one of said test nodes; memory means of a FIFO memory type connected to said node selection means, for storing a logical value at a test node selected by said node selection means, data being inhibited from being written in said memory means by executing a command of said tested circuit; and control means for controlling said node selection means and said memory means, said control means including write-in period specifying means, connected to said memory means, for specifying a period during which the logical value is written in said memory means, and said control means writing the logical values at the test nodes selected by said node selection means in said memory means each time a write-in condition is satisfied during a period specified by said write-in period specifying means and, after the end of write-in, reading out data from said memory means.
Claim 8
Dependent Claim
169 words
A logic integrated circuit comprising: a tested circuit to be inspected; a node selection means connected to test nodes of said tested circuit, for selecting one of said test nodes; memory means of a FIFO memory type connected to said node selection means, for storing a logical value at a test node selected by said node selection means, data being inhibited from being written in said memory means by executing a command of said tested circuit; and control means for controlling said node selection means and said memory means, said control means including write-in period specifying means, connected to said memory means, for specifying a period during which the logical value is written in said memory means, and said control means writing the logical values at the test nodes selected by said node selection means in said memory means each time a write-in condition is satisfied during a period specified by said write-in period specifying means and, after the end of write-in, reading out data from said memory means.
Claim 9
Dependent Claim
15 words
A logic integrated circuit according to claim 6, wherein said memory means includes shift register.
Claim 10
Dependent Claim
15 words
A logic integrated circuit according to claim 6, wherein said memory means includes a RAM.
Claim 11
Dependent Claim
20 words
A logic integrated circuit according to claim 6, wherein said memory means comprises a serial input/parallel output type memory circuit.
Claim 12
Dependent Claim
16 words
A logic integrated circuit according to claim 6, wherein said node selection means comprises a selector.
Claim 13
Dependent Claim
17 words
A logic integrated circuit according to claim 6, wherein said write-in period specifying means comprises a flip-flop.
Claim 14
Dependent Claim
31 words
A logic integrated circuit according to claim 6, wherein said write-in period specifying means comprises a flip-flop which is set or reset in response to an externally supplied control input signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-11 | 1993-06-12 | 1993-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-11 | 1997-06-12 | 1997-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-11 | 2001-06-12 | 2001-12-12 | $7700.00 | Window Closed / Lapsed |