Abstract A coincidence determination circuit capable of reducing number of elements by providing a time period during which the coincidence determination is enabled. This coincidence determination circuit comprises, a first comparison unit provided with a plurality of first bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first P-channel transistor having a gate to which a clock signal is inputted, a second P-channel transistor having a gate to which reference data of a certain bit is inputted, and a third P-channel transistor having a gate to which inverted data of the data of that bit to be compared is inputted, the first to third P-channel transistors being connected in series, respective outputs of the first bit comparison units being wired-OR connected to a first output line, said first output line serving to pull its signal level down in response to the clock signal; a second comparison unit provided with a plurality of second bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first N-channel transistor having a gate to which an inverted signal of the clock signal is inputted, a second N-channel transistor having a gate to which reference data of a certain bit is inputted, and a third N-channel transistor having a gate to which inverted data of the data of that bit to be compared is inputted, the first to third N-channel transistors being connected in series, respective outputs of the second bit comparison units being wired-OR connected to a second output line, the second output line serving to pull its level up by the inverted signal of the clock signal; and an output unit for producing a coincidence output when the first output line is at a low level and the second output line is at a high level.
A coincidence determination circuit comprising: a first comparison unit provided with a plurality of first bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first P-channel transistor having a gate to which a clock signal is inputted, a second P-channel transistor having a gate to which reference data of a certain bit is inputted, and a third P-channel transistor having a gate to which inverted data of the data of that bit to be compared is inputted, said first to third P-channel transistors being connected in series, respective outputs of said first bit comparison units being wired-OR connected to a first output line, said first output line serving to pull its signal level down in response to said clock signal; a second comparison unit provided with a plurality of second bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first N-channel transistor having a gate to which an inverted signal of said clock signal is inputted, a second N-channel transistor having a gate to which reference data of a certain bit is inputted, and a third N-channel transistor having a gate to which inverted data of the data of that bit to be compared is inputted, said first to third N-channel transistors being connected in series, respective outputs of said second bit comparison units being wired-OR connected to a second output line, said second output line serving to pull its level up by said inverted signal of said clock signal; and an output unit for producing a coincidence output when said first output line is at a low level and said second output line is at a high level.
Claim 2
Dependent Claim
281 words
A coincidence determination circuit comprising: a first comparison unit provided with a plurality of first bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first P-channel transistor having a gate to which a clock signal is inputted, a second P-channel transistor having a gate to which reference data of a certain bit is inputted, and a third P-channel transistor having a gate to which inverted data of the data of that bit to be compared is inputted, said first to third P-channel transistors being connected in series, respective outputs of said first bit comparison units being wired-OR connected to a first output line, said first output line serving to pull its signal level down in response to said clock signal; a second comparison unit provided with a plurality of second bit comparison units corresponding to a plurality of bits, each bit comparison unit comprising a first N-channel transistor having a gate to which an inverted signal of said clock signal is inputted, a second N-channel transistor having a gate to which reference data of a certain bit is inputted, and a third N-channel transistor having a gate to which inverted data of the data of that bit to be compared is inputted, said first to third N-channel transistors being connected in series, respective outputs of said second bit comparison units being wired-OR connected to a second output line, said second output line serving to pull its level up by said inverted signal of said clock signal; and an output unit for producing a coincidence output when said first output line is at a low level and said second output line is at a high level.
Claim 3
Dependent Claim
37 words
A coincidence determination circuit as set forth in claim 1, wherein said first P-channel transistor in the first comparison unit and said first N-channel transistor in the second comparison unit are used in common to respective bits.