Cmos logical circuit

Abstract

Abstract PURPOSE:To attain a CMOS exclusive OR circuit with a few hardware, by constituting the titled circuit that no inverted signal (A and A', and B and B' etc.) is required as an input signal. CONSTITUTION:When the input signals A, B are both at ''1'', transistors (TRs) M2, M3 are conductive, a voltage Vx1 at a node X1 goes to ground potential, and a TRM1 is conductive with VR1-VTHM1 >0(where VTHM1 is a threshold voltage of the TRM1), and a logic ''0'' is outputted at an output terminal W. When the signals A, B are both at ''0'', TRs M4, M5 are conductive similarly and logical ''0'' is outputted at the output terminal W. When the signal A is at ''0'' and the B is at ''1'' level, TRs M6, M9 are conductive and a voltage Vx2 at a node x2 goes to a VDD. With the condition of VR2-VTHM6<VDD, the TRM6 is conductive, the output terminal W goes to the power supply voltage VDD and logical ''1'' is outputted.

Inventors

• 👤 Hideji Koike
• 👤 秀治 小池

Bibliographic Details