Data processing device composed of four data processing modules of identical construction, with protection both against simultaneous single-bit failures in the data processing modules and against failure of a single data processing module

Claim 1

A data processing device comprising: (a) four data processing modules (100, 102, 104, 106) which each include (i) corresponding data processing means (12, 14, 16, 18) having a data path width of at least 2n bytes, where n is an integer greater than or equal to one, (ii) a respective encoder module (20, 22, 24, 26) fed by the corresponding data processing means for bytewise encoding a processing result of 2n bytes to a respective encoding result of n bytes, (iii) a respective memory module (28, 30, 32, 34) fed by the respective encoder module for storing the respective encoding result, P2 (iv) respective input decoders (54, 56, 58, 60) for receiving said encoding results in groups of four bytes and therefrom reconstituting a two-byte data word representing said processing result for presentation to the corresponding data processing means, (b) an interconnection network ((82, 84, 86, 88) fed by the respective data processing modules for applying encoding results between all data processing modules and the respective input decoders, (c) mode register means for controlling said input decoders so that they assume respective first, second and third modes, so that (i) in the first mode, said input decoders accept and digest all bytes of one of said groups, (ii) in the second mode, the input decoders accept and digest three bytes of one of said groups but reject an associated fourth byte of said group, there being four possible modes designated the second mode, and (iii) in the third mode, the input decoders accept and digest two bytes of one of said groups but reject an associated combination of two remaining byes of said group, there being six possible modes designated the third mode, and wherein said encoder modules multiply each byte of a data word by a regular matrix and add the multiplication bytes to produce a code byte, the four code bytes thus generated by the respective encoder modules constituting a code word, of a code with a minimum Hamming distance over the bits of seven, the three code bytes accepted in any second mode constituting a partial code word with a minimum Hamming distance over the bits of four, the two bytes accepted in any third mode constituting a representation of all bits of the associated processing result.