Hand-shake type data transfer control circuit

Claim 2

A handshake type control circuit for controlling data transfer at a given stage in response to a send signal, said control circuit comprising: a circuit, responsive to said send signal and an acknowledge signal fed back from a succeeding stage, for activating a transfer control signal a first time to activate data transfer at said given stage when said send signal is activated and for inactivating said transfer control signal to inactivate data transfer at said given stage when said acknowledge signal is activated, said circuit prevented from activating said transfer control signal a second time to prevent recurring data transfer at said given stage until said send signal has been reset, whereby parasitic oscillation is prevented.

Claim 3

The control circuit of claim 1 wherein said circuit comprises a flip-flop having two two-input only NAND gates.

Claim 6

A handshake type control circuit for controlling data transfer at a given stage in response to a send signal, said control circuit comprising: receiving means, responsive to at least four inputs including said send signal, a feedback signal, an acknowledge signal fed back from a succeeding stage, and a second control signal, for activating a first control signal when said send signal is activated and said feedback signal, said acknowledge signal, and said second control signal are inactivated and for inactivating said first control signal when said send signal is inactivated or when any one of said feedback signal, said acknowledge signal, and said second signal is activated; a first circuit, responsive to said first control signal and said acknowledge signal, for activating a transfer control signal to activate data transfer at said given stage and said feedback signal when said first control signal is activated and for inactivating said transfer control signal to inactive data transfer at said given stage when said acknowledge signal is activated; and a second circuit, responsive to said first control signal and said send signal, for activating said second control signal when said first control signal is activated and for inactivating said second control signal when said send signal is inactivated so that said transfer control signal can be activated only once each time said send signal is activated and parasitic oscillation is prevented.

Claim 7

A handshake type control circuit for controlling data transfer at a given stage in response to a send signal, said control circuit comprising: receiving means, responsive to at least four inputs including said send signal, a feedback signal, an acknowledge signal fed back from a succeeding stage, and a second control signal, for activating a first control signal when said send signal is activated and said feedback signal, said acknowledge signal, and said second control signal are inactivated and for inactivating said first control signal when said send signal is inactivated or when any one of said feedback signal, said acknowledge signal, and said second signal is activated; a first circuit, responsive to said first control signal and said acknowledge signal, for activating a transfer control signal to activate data transfer at said given stage and said feedback signal when said first control signal is activated and for inactivating said transfer control signal to inactive data transfer at said given stage when said acknowledge signal is activated; and a second circuit, responsive to said first control signal and said send signal, for activating said second control signal when said first control signal is activated and for inactivating said second control signal when said send signal is inactivated so that said transfer control signal can be activated only once each time said send signal is activated and parasitic oscillation is prevented.

Claim 8

The control circuit of claim 4 wherein said receiving means comprises a NAND gate.

Claim 9

The control circuit of claim 4 wherein said first circuit comprises a flip-flop.

Claim 10

The control circuit of claim 4 wherein said second circuit comprises a flip-flop.

Claim 11

The control circuit of claim 4 wherein said first and second circuits each comprises two two-input only NAND gates.

Claim 12

The control circuit of claim 4 wherein said receiving means, said first circuit, and said second circuit include NAND gates each of which has only two input terminals.

Claim 13

The control circuit of claim 4 wherein said control circuit is a MOS type circuit.

Claim 14

The control circuit of claim 4 wherein said acknowledge signal is activated after processing at said succeeding stage has been completed.

Claim 15

The control circuit of claim 4 wherein said acknowledge signal is activated after said send signal is received at said succeeding stage.

Claim 16

The control circuit of claim 4 wherein said second circuit is disposed outside a communication path between said given stage and said succeeding stage.

Claim 17

A handshake type data transfer system for transferring data in response to a data transfer request signal, comprising: a plurality of consecutive pipelined transfer stages, each having a data transfer circuit and a corresponding control circuit, said stages communicating over a send line and an acknowledge line; a given stage having at least one said control circuit which includes: receiving means, responsive to at least four inputs including a send signal, a feedbak signal, an acknowledge signal fed back from a succeeding stage, and a second control signal, for activating a first control signal when said send signal is activated and said feedback signal, said acknowledge signal, and said second control signal are inactivated and for inactivating said first control signal when said send signal is inactivated or when any one of said feedback signal, said acknowledge signal, and said second control signal is activated, a first circuit, responsive to said first control signal and said acknowledge signal, for activating a transfer control signal to activate data transfer at said given stage and said feedback signal when said first control signal is activated and for inactivating said transfer control signal to inactivate data transfer at said given stage when said acknowledge signal is activated, and a second circuit, responsive to said first control signal and said send signal, for activating said second control signal when said first control signal is activated and for inactivating said second control signal when said send signal is inactivated so that said transfer control signal can be activated only once in response to each activated send signal and parasitic oscillation is prevented, wherein said acknowledge signal received at said given stage is said second control signal produced by said succeeding stage and said send signal received at said succeeding stage is provided by said control circuit of said given stage; and said data transfer request signal being said send signal received at an initial stage of said stages.

Claim 18

A handshake type data transfer system for transferring data in response to a data transfer request signal, comprising: a plurality of consecutive pipelined transfer stages, each having a data transfer circuit and a corresponding control circuit, said stages communicating over a send line and an acknowledge line; a given stage having at least one said control circuit which includes: receiving means, responsive to at least four inputs including a send signal, a feedbak signal, an acknowledge signal fed back from a succeeding stage, and a second control signal, for activating a first control signal when said send signal is activated and said feedback signal, said acknowledge signal, and said second control signal are inactivated and for inactivating said first control signal when said send signal is inactivated or when any one of said feedback signal, said acknowledge signal, and said second control signal is activated, a first circuit, responsive to said first control signal and said acknowledge signal, for activating a transfer control signal to activate data transfer at said given stage and said feedback signal when said first control signal is activated and for inactivating said transfer control signal to inactivate data transfer at said given stage when said acknowledge signal is activated, and a second circuit, responsive to said first control signal and said send signal, for activating said second control signal when said first control signal is activated and for inactivating said second control signal when said send signal is inactivated so that said transfer control signal can be activated only once in response to each activated send signal and parasitic oscillation is prevented, wherein said acknowledge signal received at said given stage is said second control signal produced by said succeeding stage and said send signal received at said succeeding stage is provided by said control circuit of said given stage; and said data transfer request signal being said send signal received at an initial stage of said stages.

Claim 19

The transfer system of claim 14 wherein at least one said data transfer circuit comprises a latch circuit.

Claim 20

The transfer system of claim 14 wherein at least one said data transfer circuit is coupled to means for processing data.

Claim 21

The transfer system of claim 14 wherein said acknowledge signal is activated after processing at said succeeding stage has been completed.

Claim 22

The transfer system of claim 14 wherein said second control signal is provided as an acknowledge signal by said given stage to a preceding stage.

Claim 23

The transfer system of claim 14 wherein said given stage further includes means, coupled to said control circuit, for delaying the transfer of said send signal from said given stage to said succeeding stage for a predetermined time.

Claim 24

A handshake type pipelined data processing system for transferring data in response to a data transfer request signal, said data processing system having a plurality of consecutive stages including a given stage which comprises: a processor; a data transfer circuit for transferring data to said processor; a control circuit for controlling data transfer at said given stage in response to a send signal, said control circuit comprising: receiving means, responsive to at least four inputs including said send signal, a feedback signal, an acknowledge signal fed back from a succeeding stage, and a second control signal, for activating a first control signal when said send signal is activated and said feedback signal, said acknowledge signal, and said second control signal are inactivated and for inactivating said first control signal when said send signal in inactivated or when any one of said feedback signal, said acknowledge signal, and said second control signal is activated, a first circuit, responsive to said first control signal and said acknowledge signal, for activating a transfer control signal to activate data transfer at said given stage and said feedback signal when said first control signal is activated and for inactivating said transfer control signal to inactivate data transfer at said given when said acknowledge signal is activated, and a second circuit, responsive to said first control signal and said send signal, for activating a second control signal when said first control signal is activated and for inactivating said second control signal when said send signal is inactivated so that said transfer control signal can be activated only once in response to each activated send signal and parasitic oscillation is prevented, wherein said acknowledge signal received at said given stage is said second control signal produced by said succeeding stage and said send signal received at said succeeding stage is provided by said control circuit of said given stage; and said data transfer request signal being said send signal received at an initial stage of said stages.

Claim 25

A handshake type pipelined data processing system for transferring data in response to a data transfer request signal, said data processing system having a plurality of consecutive stages including a given stage which comprises: a processor; a data transfer circuit for transferring data to said processor; a control circuit for controlling data transfer at said given stage in response to a send signal, said control circuit comprising: receiving means, responsive to at least four inputs including said send signal, a feedback signal, an acknowledge signal fed back from a succeeding stage, and a second control signal, for activating a first control signal when said send signal is activated and said feedback signal, said acknowledge signal, and said second control signal are inactivated and for inactivating said first control signal when said send signal in inactivated or when any one of said feedback signal, said acknowledge signal, and said second control signal is activated, a first circuit, responsive to said first control signal and said acknowledge signal, for activating a transfer control signal to activate data transfer at said given stage and said feedback signal when said first control signal is activated and for inactivating said transfer control signal to inactivate data transfer at said given when said acknowledge signal is activated, and a second circuit, responsive to said first control signal and said send signal, for activating a second control signal when said first control signal is activated and for inactivating said second control signal when said send signal is inactivated so that said transfer control signal can be activated only once in response to each activated send signal and parasitic oscillation is prevented, wherein said acknowledge signal received at said given stage is said second control signal produced by said succeeding stage and said send signal received at said succeeding stage is provided by said control circuit of said given stage; and said data transfer request signal being said send signal received at an initial stage of said stages.

Claim 26

A handshake type pipelined data processing system having a plurality of consecutive stages for transferring data in response to a data transfer request signal, a given stage including a data transfer circuit and a control circuit coupled thereto for controlling data transfer in response to a send signal, said control circuit comprising: a NAND gate having a first input for receiving said send signal, a second input for receiving a feedback signal, a third input for receiving an acknowledge signal fed back from a succeeding stage, and a fourth input for receiving a second control signal, said NAND gate activating a first control signal at the output when said send signal is activated and said feedback signal, said acknowledge signal, and said second control signal are inactivated, said NAND gate inactivating said first control signal at the output when said send signal is inactivated or when any one of said feedback signal, said acknowledge signal, and said second control signal is activated; a first flip-flop having a first input coupled to the output of said NAND gate and a second input for receiving said acknowledge signal, said first flip-flop activating a transfer control signal to activate data transfer through said data transfer circuit and said feedback signal when said first control signal is activated, said first flip-flop inactivating said transfer control signal to inactive data transfer through said data transfer circuit when said acknowledge signal is activated; and a second flip-flop having a first input coupled to the output of said NAND gate and a second input for receiving said send signal, said second flip-flop activating said second control signal when said first control signal is activated, said second flip-flop inactivating said second control signal when said send signal is inactivated so that said transfer control signal can be activated only once for each received activated send signal and parasitic oscillation is prevented; wherein said acknowledge signal received at said given stage is said second control signal produced by said succeeding stage and said send signal received at said succeeding stage is provided by said control circuit of said given stage; and said data transfer request signal being said signal received at an initial stage of said stages.

Claim 27

A handshake type pipelined data processing system having a plurality of consecutive stages for transferring data in response to a data transfer request signal, a given stage including a data transfer circuit and a control circuit coupled thereto for controlling data transfer in response to a send signal, said control circuit comprising: a NAND gate having a first input for receiving said send signal, a second input for receiving a feedback signal, a third input for receiving an acknowledge signal fed back from a succeeding stage, and a fourth input for receiving a second control signal, said NAND gate activating a first control signal at the output when said send signal is activated and said feedback signal, said acknowledge signal, and said second control signal are inactivated, said NAND gate inactivating said first control signal at the output when said send signal is inactivated or when any one of said feedback signal, said acknowledge signal, and said second control signal is activated; a first flip-flop having a first input coupled to the output of said NAND gate and a second input for receiving said acknowledge signal, said first flip-flop activating a transfer control signal to activate data transfer through said data transfer circuit and said feedback signal when said first control signal is activated, said first flip-flop inactivating said transfer control signal to inactive data transfer through said data transfer circuit when said acknowledge signal is activated; and a second flip-flop having a first input coupled to the output of said NAND gate and a second input for receiving said send signal, said second flip-flop activating said second control signal when said first control signal is activated, said second flip-flop inactivating said second control signal when said send signal is inactivated so that said transfer control signal can be activated only once for each received activated send signal and parasitic oscillation is prevented; wherein said acknowledge signal received at said given stage is said second control signal produced by said succeeding stage and said send signal received at said succeeding stage is provided by said control circuit of said given stage; and said data transfer request signal being said signal received at an initial stage of said stages.

Claim 28

A handshake type control circuit for controlling data unlatching and latching at a given stage in response to a send signal, said control circuit comprising: means, responsive to said send signal, for setting a latch control signal a first time when said send signal is set and for resetting said latch control signal in response to said send signal received at a succeeding stage; and means, responsive to said send signal, for preventing said means for setting and resetting from setting said latch control signal a second time until said send signal has been reset, whereby parasitic oscillation is prevented.

Claim 29

A handshake type control circuit for controlling data unlatching and latching at a given stage in response to a send signal, said control circuit comprising: means, responsive to said send signal, for setting a latch control signal a first time when said send signal is set and for resetting said latch control signal in response to said send signal received at a succeeding stage; and means, responsive to said send signal, for preventing said means for setting and resetting from setting said latch control signal a second time until said send signal has been reset, whereby parasitic oscillation is prevented.

Claim 30

A handshake type data latch system for controlling data unlatching and latching in response to a send signal, comprising: a first and a second stage coupled to one another, each stage having a data latch circuit controlled by a latch control signal pair including a first latch control signal and a second latch control signal which is the complement of said first latch control signal and a corresponding control circuit coupled to said data latch circuit for setting and resetting said first latch control signal; said control circuit including: receiving means, responsive to at least four inputs including said send signal, a feedback signal, an acknowledge signal, and a second control signal, for resetting a first control signal when all of said four inputs are set and for setting said first control signal when any one of said four inputs is reset, a first circuit, responsive to said first control signal and said acknowledge signal, for setting said first latch control signal and resetting said feedback signal when said first control signal is reset and for resetting said first latch control signal when said acknowledge signal is reset, and a second circuit, responsive to said first control signal and said send signal, for resetting said second control signal when said first control signal is reset and for setting said second control signal when said send signal is reset so that said first latch control signal can be set only once in response to each set send signal and parasitic oscillation is prevented; said acknowledge signal received at said first stage being said second control signal produced by said second stage; and said send signal received at said second stage provided by said control circuit of said first stage.

Claim 31

A handshake type data latch system for controlling data unlatching and latching in response to a send signal, comprising: a first and a second stage coupled to one another, each stage having a data latch circuit controlled by a latch control signal pair including a first latch control signal and a second latch control signal which is the complement of said first latch control signal and a corresponding control circuit coupled to said data latch circuit for setting and resetting said first latch control signal; said control circuit including: receiving means, responsive to at least four inputs including said send signal, a feedback signal, an acknowledge signal, and a second control signal, for resetting a first control signal when all of said four inputs are set and for setting said first control signal when any one of said four inputs is reset, a first circuit, responsive to said first control signal and said acknowledge signal, for setting said first latch control signal and resetting said feedback signal when said first control signal is reset and for resetting said first latch control signal when said acknowledge signal is reset, and a second circuit, responsive to said first control signal and said send signal, for resetting said second control signal when said first control signal is reset and for setting said second control signal when said send signal is reset so that said first latch control signal can be set only once in response to each set send signal and parasitic oscillation is prevented; said acknowledge signal received at said first stage being said second control signal produced by said second stage; and said send signal received at said second stage provided by said control circuit of said first stage.

Claim 32

The handshake type data latch system of claim 23 wherein said send signal received at said second stage is said first latch control signal.

Claim 33

The handshake type data latch system of claim 23 wherein said first circuit means of said control circuit of said first stage provides a third control signal as said send signal received at said second stage, the complement of said third control signal provided as said second latch control signal.