Patent US4881167A successfully refreshed from Google Patents.
US4881167A
Expired / Lapsed
US
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Data memory system
Assignee: Hitachi Ltd
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Filing: 1989-03-02
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Granted: 1989-11-14
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Expires: 2009-03-02
Abstract
Abstract A data memory system includes a plurality of buffer regions each having a constant size so that serial data may be stored by linking the buffer regions. A descripter provided to correspond to each of the buffer regions includes memory region addressing information indicating the head address of the corresponding buffer region, data delimiting information indicating whether or not the data to be stored is terminated in the corresponding buffer region, and chain information indicating the head address of a next subsequent descripter.
Inventors
- 👤 Hisao Sasaki
- 👤 Matsuaki Terada
- 👤 Susumu Matsui
- 👤 Kenji Kawakita
- 👤 Jiro Kashio
- 👤 Shiro Baba
- 👤 Yasushi Akao
- 👤 Toshio Okochi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:43
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/90; H04L49/901; G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F5/00; G06F5/06; H04L49/9021; G06F2205/00; G06F2205/06; G06F2205/064
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
127 words
A data memory system comprising: a plurality of buffer regions, each buffer region having a respectively predetermined memory capacity for storing data; a like plurality of descripter regions, each descripter region corresponding with a respective one of said plurality of buffer regions, each descripter region including a first portion for containing buffer region addressing information, designating the address of the corresponding one of said plurality of buffer regions, and a second portion for containing chain information, designating the address of another descripter region to be linked to said each descripter region so that said each descripter region is capable of being linked to another descripter region, allowing data stored in said buffer regions to be linked on the basis of the chain information in said descripter regions.
Claim 2
Dependent Claim
127 words
A data memory system comprising: a plurality of buffer regions, each buffer region having a respectively predetermined memory capacity for storing data; a like plurality of descripter regions, each descripter region corresponding with a respective one of said plurality of buffer regions, each descripter region including a first portion for containing buffer region addressing information, designating the address of the corresponding one of said plurality of buffer regions, and a second portion for containing chain information, designating the address of another descripter region to be linked to said each descripter region so that said each descripter region is capable of being linked to another descripter region, allowing data stored in said buffer regions to be linked on the basis of the chain information in said descripter regions.
Claim 3
Dependent Claim
38 words
A data memory system according to claim 1, wherein each descripter region further includes a third portion adapted for containing data delimiting information indicating that the corresponding buffer region contains data including an end of data frame indication.
Claim 4
Dependent Claim
48 words
A data memory system according to claim 2, wherein each first portion contains buffer region addressing information designating the head address of said corresponding one of said plurality of buffer regions, and wherein each second portion contains chain information identifying the head address of said another descripter region.
Claim 5
Dependent Claim
148 words
A memory system comprising: a memory including a plurality of addressable buffer regions, each buffer region having a respectively predetermined memory capacity for storing data, and a like plurality of descripter regions, each descripter region corresponding with a respective one of said plurality of buffer regions; and memory access means for executing data writing and data reading operations with said memory; each of said descripter regions including a first portion for containing buffer region addressing information, designating the address of the corresponding one of said plurality of buffer regions, and a second portion for containing chain information, designating the address of another descripter region to be linked to said each descripter region so that said each descripter region is capable of being linked to another descripter region, allowing data stored in said buffer regions to be linked on the basis of the chain information in said descripter regions.
Claim 6
Dependent Claim
148 words
A memory system comprising: a memory including a plurality of addressable buffer regions, each buffer region having a respectively predetermined memory capacity for storing data, and a like plurality of descripter regions, each descripter region corresponding with a respective one of said plurality of buffer regions; and memory access means for executing data writing and data reading operations with said memory; each of said descripter regions including a first portion for containing buffer region addressing information, designating the address of the corresponding one of said plurality of buffer regions, and a second portion for containing chain information, designating the address of another descripter region to be linked to said each descripter region so that said each descripter region is capable of being linked to another descripter region, allowing data stored in said buffer regions to be linked on the basis of the chain information in said descripter regions.
Claim 7
Dependent Claim
18 words
A memory system according to claim 4, wherein said memory access means includes a direct memory access controller.
Claim 8
Dependent Claim
37 words
A memory system according to claim 5, wherein said direct memory access controller includes means for storing the address of the descripter region corresponding with the buffer region with which data is to be written or read.
Claim 9
Dependent Claim
36 words
A memory system according to claim 6, wherein said direct access memory controller further includes means for transmitting and receiving the data to be stored in said each buffer region in serial communication of data frames.
Claim 10
Dependent Claim
49 words
A memory system according to claim 4, wherein each descripter region further includes a third portion adapted for containing data delimiting information indicating that the corresponding buffer region contains data including an end of data frame indication, indicating that there are no subsequent linked buffer regions containing linked data.
Claim 11
Dependent Claim
185 words
A memory system comprising: memory means including a first memory region for storing at least part of a data communication, a second memory region for storing at least part of a data communication, a third memory region for storing first descripter information relating to said first memory region, and a fourth memory region for storing second descripter information relating to said second memory region, said first descripter information including first address information for designating the address of said first memory region, second address information for designating the address of said fourth memory region, and data delimiting information indicating whether said first memory region contains the end of the data communication stored therein, and said second descripter information including third address information for designating the address of said second memory region; and memory access means for interrogating said third memory region, obtaining the first address information, accessing said first memory region to access the data communication stored therein, obtaining the second address information, interrogating said fourth memory region, obtaining the third address information, and accessing said second memory region to access the data communication stored therein.
Claim 12
Dependent Claim
185 words
A memory system comprising: memory means including a first memory region for storing at least part of a data communication, a second memory region for storing at least part of a data communication, a third memory region for storing first descripter information relating to said first memory region, and a fourth memory region for storing second descripter information relating to said second memory region, said first descripter information including first address information for designating the address of said first memory region, second address information for designating the address of said fourth memory region, and data delimiting information indicating whether said first memory region contains the end of the data communication stored therein, and said second descripter information including third address information for designating the address of said second memory region; and memory access means for interrogating said third memory region, obtaining the first address information, accessing said first memory region to access the data communication stored therein, obtaining the second address information, interrogating said fourth memory region, obtaining the third address information, and accessing said second memory region to access the data communication stored therein.
Claim 13
Dependent Claim
53 words
A memory system according to claim 9, wherein said first descripter information further includes first data length information indicating the length of the data stored in said first memory region, and said second descripter information further includes second data length information indicating the length of the data stored in said second memory region.
Claim 14
Dependent Claim
19 words
A memory system according to claim 10, wherein said first data length is different from said second data length.
Claim 15
Dependent Claim
48 words
A memory system according to claim 9, wherein said first address information includes the head address of said first memory region, said second address information includes the head address of said fourth memory region, and said third address information includes the head address of said second memory region.
Claim 16
Dependent Claim
26 words
A memory system according to claim 9, wherein said first memory region has a capacity substantially the same as the capacity of said second memory region.
Claim 17
Dependent Claim
35 words
A memory system according to claim 9, wherein each of said first memory region and said second memory region is adapted to transmit and receive data in serial communication of data frames for storage therein.
Claim 18
Dependent Claim
193 words
A microprocessor system comprising: memory means including a first memory region for storing at least part of a data communication, a second memory region for storing at least part of a data communication, a third memory region for storing first descripter information relating to said first memory region, and a fourth memory region for storing second descripter information relating to said second memory region, said first descripter information including first address information for designating the address of said first memory region, second address information for designating the address of said fourth memory region, and data delimiting information indicating whether said first memory region contains the end of the data communication stored therein, and said second descripter information including third address information for designating the address of said second memory region; memory access means for interrogating said third memory region, obtaining the first address information, accessing said first memory region to access the data communication stored therein, obtaining the second address information, interrogating said fourth memory region, obtaining the third address information, and accessing said second memory region to access the data communication stored therein; and a CPU for controlling said memory access means.
Claim 19
Dependent Claim
193 words
A microprocessor system comprising: memory means including a first memory region for storing at least part of a data communication, a second memory region for storing at least part of a data communication, a third memory region for storing first descripter information relating to said first memory region, and a fourth memory region for storing second descripter information relating to said second memory region, said first descripter information including first address information for designating the address of said first memory region, second address information for designating the address of said fourth memory region, and data delimiting information indicating whether said first memory region contains the end of the data communication stored therein, and said second descripter information including third address information for designating the address of said second memory region; memory access means for interrogating said third memory region, obtaining the first address information, accessing said first memory region to access the data communication stored therein, obtaining the second address information, interrogating said fourth memory region, obtaining the third address information, and accessing said second memory region to access the data communication stored therein; and a CPU for controlling said memory access means.
Claim 20
Dependent Claim
53 words
A microprocessor system according to claim 15, wherein said first descripter information further includes first data length information indicating the length of the data stored in said first memory region, and said second descripter information further includes second data length information indicating the length of the data stored in said second memory region.
Claim 21
Dependent Claim
19 words
A microprocessor system according to claim 16, wherein said first data length is different from said second data length.
Claim 22
Dependent Claim
48 words
A microprocessor system according to claim 15, wherein said first address information includes the head address of said first memory region, said second address information includes the head address of said fourth memory region, and said third address information includes the head address of said second memory region.
Claim 23
Dependent Claim
26 words
A microprocessor system according to claim 15, wherein said first memory region has a capacity substantially the same as the capacity of said second memory region.
Claim 24
Dependent Claim
35 words
A microprocessor system according to claim 15, wherein each of said first memory region and said second memory region is adapted to transmit and receive data in serial communication of data frames for storage therein.
Claim 25
Independent Claim
168 words
A method of operating a memory system including a first memory region storing at least part of a first data communicating having a first data length, a second memory region storing at least part of a second data communication having a second data length, a third memory region storing first descripter information relating to the first memory region, and a fourth memory region storing second descripter information relating to the second memory region, the first descripter information including first address information designating the address of the first memory region and second address information designating the address of the fourth memory region and the second descripter information including third address information designating the address of the second memory region, said method comprising the steps of: interrogating the third memory region; obtaining the first address information; accessing the first memory region; obtaining the second address information; interrogating the fourth memory region; obtaining the third address information; and accessing the second memory region to read data therefrom or write data thereinto.
Claim 26
Independent Claim
168 words
A method of operating a memory system including a first memory region storing at least part of a first data communicating having a first data length, a second memory region storing at least part of a second data communication having a second data length, a third memory region storing first descripter information relating to the first memory region, and a fourth memory region storing second descripter information relating to the second memory region, the first descripter information including first address information designating the address of the first memory region and second address information designating the address of the fourth memory region and the second descripter information including third address information designating the address of the second memory region, said method comprising the steps of: interrogating the third memory region; obtaining the first address information; accessing the first memory region; obtaining the second address information; interrogating the fourth memory region; obtaining the third address information; and accessing the second memory region to read data therefrom or write data thereinto.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-13 | 1993-05-15 | 1993-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-13 | 1997-05-15 | 1997-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-13 | 2001-05-15 | 2001-11-14 | $7700.00 | Window Closed / Lapsed |