Patent US3615552A successfully refreshed from Google Patents.
Patent US4881108A successfully refreshed from Google Patents.
US4881108A
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Semiconductor device
Assignee: Toshiba Corp
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Filing: 1988-03-24
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Granted: 1989-11-14
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Expires: 2008-03-24
Abstract
Abstract A semiconductor device includes source and drain regions, a charge accumulation region, and a control gate in a channel region between the source and drain regions. The charge accumulation region is located on the side surface of the control gate.
Inventors
- 👤 Kuniyoshi Yoshikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:19
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01346; H10D30/00; H10D30/01; H10D30/021; H10D30/0413; H10D30/60; H10D30/69; H10D64/60; H10D64/66; H10D64/68; H10D64/681; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
94 words
A semiconductor device comprising: first and second regions separately provided from each other on a surface region of a semiconductor substrate, said first and second regions serving as source and drain regions, respectively, a charge accumulation region, and a gate provided on a channel region between said first and second regions, said charge accumulation region disposed on said channel region on a side surface of said gate and not on a top surface of said gate, said charge accumulation region including a silicon nitride interposed between said gate and said first or second region.
Claim 2
Dependent Claim
94 words
A semiconductor device comprising: first and second regions separately provided from each other on a surface region of a semiconductor substrate, said first and second regions serving as source and drain regions, respectively, a charge accumulation region, and a gate provided on a channel region between said first and second regions, said charge accumulation region disposed on said channel region on a side surface of said gate and not on a top surface of said gate, said charge accumulation region including a silicon nitride interposed between said gate and said first or second region.
Claim 3
Dependent Claim
48 words
A semiconductor device as set forth in claim 1, wherein said charge accumulation region is a silicon nitride having a three-layer stacking film comprising a first silicon oxide film, a silicon nitride film, and a second silicon oxide film all formed on said side surface of said gate.
Claim 4
Dependent Claim
26 words
A semiconductor device as set forth in claim 1, wherein said charge accumulation region is located only in the vicinity of said first or second region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-13 | 1993-05-15 | 1993-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-13 | 1997-05-15 | 1997-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-13 | 2001-05-15 | 2001-11-14 | $7700.00 | Window Closed / Lapsed |