Semiconductor integrated circuit devices and methods for testing same

Claim 2

A semiconductor integrated circuit device, comprising: (i) a semiconductor integrated circuit chip having a plurality of signal wires; (ii) a plurality of electron beam test terminals electrically connected to said signal wires, said electron beam test terminals being concentrated in at least one selected area of said semiconductor integrated circuit chip; (iii) first connecting wires being connected to ones of said signal wires and extending into said selected area; (vi) second connecting wires being connected to others of said signal wires, said second connecting wires having a level lower than that of said first connecting wires, extending into said selected area with a length longer than that of said first connecting wires, and being respectively positioned between said first connecting wires in said selected area; (v) an insulating layer disposed between said first and second connecting wires, said insulating layer having apertures at which tip portions of said second connecting wires are exposed; and (vi) conductive layers formed in the same plane and made from the same material as said first connecting wires, said conductive layers contacting said second connecting wires through said apertures and forming a first group of said electron beam test terminals, and portions of said first connecting wires in said selected area forming a second group of said electron beam test terminals.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said electron beam test terminals are directed to said selected area from at least two opposite directions.

Claim 4

A semiconductor integrated circuit device according to claim 1, wherein said electron beam test terminals are directed to said selected area from four directions.

Claim 5

A semiconductor integrated device according to claim 1, wherein said selected area is rectangular in shape.

Claim 6

A semiconductor integrated circuit device according to claim 1, wherein said selected area is formed in a circuit area of said semiconductor integrated circuit chip.

Claim 7

A semiconductor integrated circuit device according to claim 1, further comprising: a test cell having said selected area thereon and inserted into a logic cell line on said chip, said electron beam test terminals being concentrated within said selected area from two opposite sides along said logic cell line.

Claim 8

A semiconductor integrated circuit device according to claim 1, wherein said first connecting wires and conductive layers are made from Al.

Claim 9

A semiconductor integrated circuit device, comprising: (i) a semiconductor integrated circuit chip having a plurality of signal wires; (ii) a plurality of electron beam test terminals electrically connected to said signal wires, said electron beam test terminals being concentrated in at least one selected area of said semiconductor integrated circuit chip and said selected area being rectangular in shape; (iii) first connecting wires being connected to one of said signal wires and extending into said selected area; (iv) second connecting wires being connected to others of said signal wires, said second connecting wires having a level lower than that of said first connecting wires, extending into said selected area with a longer length than that of said first connecting wires in said selected area; (v) an insulating layer disposed between said first and second connecting wires, said insulating layer having apertures at which tip portions of said second connecting wires are exposed; and (vi) conductive layers formed in a same plane and made from a same material as said first connecting wires, said conductive layers contacting said second connecting wires through said apertures and forming a first group of said electron beam test terminals, and portions of said first connecting wires in said selected area forming a second group of said electron beam test terminals, wherein said first and second connecting wires are both extended into said selected area from at least the same two opposite sides, and said first group of said electron beam test terminals being arranged in a matrix form in a region where said electron beam test terminals of said second group from said opposite two sides being configured to face each other.

Claim 10

A semiconductor integrated circuit device, comprising: (i) a semiconductor integrated circuit chip having a plurality of signal wires; (ii) a plurality of electron beam test terminals electrically connected to said signal wires, said electron beam test terminals being concentrated in at least one selected area of said semiconductor integrated circuit chip and said selected area being rectangular in shape; (iii) first connecting wires being connected to one of said signal wires and extending into said selected area; (iv) second connecting wires being connected to others of said signal wires, said second connecting wires having a level lower than that of said first connecting wires, extending into said selected area with a longer length than that of said first connecting wires in said selected area; (v) an insulating layer disposed between said first and second connecting wires, said insulating layer having apertures at which tip portions of said second connecting wires are exposed; and (vi) conductive layers formed in a same plane and made from a same material as said first connecting wires, said conductive layers contacting said second connecting wires through said apertures and forming a first group of said electron beam test terminals, and portions of said first connecting wires in said selected area forming a second group of said electron beam test terminals, wherein said first and second connecting wires are both extended into said selected area from at least the same two opposite sides, and said first group of said electron beam test terminals being arranged in a matrix form in a region where said electron beam test terminals of said second group from said opposite two sides being configured to face each other.

Claim 11

A semiconductor integrated circuit device according to claim 8, wherein said selected area is formed in a circuit area of said semiconductor integrated circuit chip.

Claim 12

A semiconductor integrated circuit device according to claim 8, wherein said first connecting wires and conductive layers are made from aluminum.

Claim 13

A semiconductor integrated circuit device according to claim 8, further comprising: a test cell having said selected area thereon and inserted into a logic cell line on said chip, said test terminals being concentrated within said selected area from two opposite sides along said logic cell line.

Claim 14

A semiconductor integrated circuit device, comprising: (i) a semiconductor integrated circuit chip having a plurality of signal wires; (ii) a plurality of electron beam test terminals electrically connected to said signal wires, said electron beam test terminals being concentrated in at least one selected area of said semiconductor integrated circuit chip and said selected area having four different sides; (iii) first connecting wires being connected to one of said signal wires and extending into said selected area; (iv) second connecting wires being connected to others of said signal wires, said second connecting wires having a level lower than that of said first connecting wires, and extending into said selected area with a longer length than that of said first connecting wires in said selected area; (v) an insulating layer disposed between said first and second connecting wires, said insulating layer having apertures at which tip portions of said second connecting wires are exposed; and (vi) conductive layers formed in a same plane and made from a same material as said first connecting wires, said conductive layers contacting said second connecting wires through said apertures and forming a first group of said electron beam test terminals, and portions of said first connecting wires in said selected area forming a second group of said electron beam test terminals, wherein said first and second connecting wires are both extended into said selected area from at least the same two opposite sides, and said first group of said electron beam test terminals being arranged in parallel lines, in a region where said electron beam test terminals of said second group extended from said opposite two sides and being configured to face each other.

Claim 15

A semiconductor integrated circuit device, comprising: (i) a semiconductor integrated circuit chip having a plurality of signal wires; (ii) a plurality of electron beam test terminals electrically connected to said signal wires, said electron beam test terminals being concentrated in at least one selected area of said semiconductor integrated circuit chip and said selected area having four different sides; (iii) first connecting wires being connected to one of said signal wires and extending into said selected area; (iv) second connecting wires being connected to others of said signal wires, said second connecting wires having a level lower than that of said first connecting wires, and extending into said selected area with a longer length than that of said first connecting wires in said selected area; (v) an insulating layer disposed between said first and second connecting wires, said insulating layer having apertures at which tip portions of said second connecting wires are exposed; and (vi) conductive layers formed in a same plane and made from a same material as said first connecting wires, said conductive layers contacting said second connecting wires through said apertures and forming a first group of said electron beam test terminals, and portions of said first connecting wires in said selected area forming a second group of said electron beam test terminals, wherein said first and second connecting wires are both extended into said selected area from at least the same two opposite sides, and said first group of said electron beam test terminals being arranged in parallel lines, in a region where said electron beam test terminals of said second group extended from said opposite two sides and being configured to face each other.

Claim 16

A semiconductor integrated circuit device according to claim 12, wherein said selected area is formed in a circuit area of said semiconductor integrated circuit chip.

Claim 17

A semiconductor integrated circuit device according to claim 12, wherein said first connecting wires and conductive wires are made from aluminum.

Claim 18

A semiconductor integrated circuit device according to claim 12, further comprising: a test cell having said selected area thereon and inserted into a logic cell line on said chip, said test terminals being concentrated within said selected area from two opposite sides along said logic cell line.