Patent US4879720A successfully refreshed from Google Patents.
US4879720A
Expired / Lapsed
US
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Decoder ring system
Assignee: MA Com Government Systems Inc
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Filing: 1988-03-10
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Granted: 1989-11-07
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Expires: 2008-03-10
Abstract
Abstract A decoding system capable of outputting Viterbi-decoding-algorithm-decoded data at a predetermined rate that is greater than a given rate at which coded data is processed in accordance with said algorithm to produce the decoded data. The system includes a data input bus; a data output bus; a ring of decoders, with each decoder being coupled to the input bus for receiving coded data from the input bus and coupled to the output bus for providing decoded data onto the output bus. Each of the decoders in the ring includes an input buffer, timing controller, decoding processor and output buffer. The input buffer responds to a start-input signal from a preceding decoder in the ring by buffering a block of the received coded data. The timing contoller provides a start-input signal to a succeeding decoder in the ring at such time as to cause the succeeding decoder to receive a block of coded data from the input bus that overlaps the block of coded data received from the input bus by the instant said decoder. The decoding processor processes the buffered block of coded data at a given rate to produce decoded data. The output buffer buffers the block of decoded data. The timing controller also responds to a start-up signal provided by a preceding decoder in the ring by causing the buffered decoded data to be provided onto the data output bus at a predetermined rate that is greater than the given rate at which the coded data is processed to produce the decoded data; and further provides a start-output signal to the succeeding decoder in the ring to cause the succeeding decoder to provide a portion of the buffered decoded data therein onto the data output bus at a predetermined rate and at such time as to be continuous from and not overlap the portion of the buffered decoded provided onto the output data bus from the instant said decoder.
Inventors
- 👤 William A. Shumate
- 👤 Daniel R. Kindred
- 👤 Franklin P. Antonio
- 👤 Steven H. Gardner
- 👤 Krishnanand Kelkar
- 👤 Thomas R. Bilotta
- 👤 Steven L. Rogers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:34
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/37; H03M13/39; H03M13/41
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
317 words
A decoding system capable of outputting Viterbi-decoding-algorithmdecoded data at a predetermined rate that is greater than a given rate at which coded data is processed in accordance with said algorithm by a single decoder to produce the decoded data, comprising a data input bus; a data output bus; a ring of decoders, with each decoder coupled to the input bus for receiving coded data from the input bus and coupled to the output bus for providing decoded data onto the output bus; wherein each said decoder includes an input buffer for responding to a start-input signal from a preceding decoder in the ring by buffering a block of the received coded data; means for providing a start-input signal to a succeeding decoder in the ring at such time as to cause the succeeding decoder to receive a block of coded data from the input bus that overlaps the block of coded data received from the input bus by the instant said decoder; processing means for processing the buffered block of coded data in accordance with a Viterbi decoding algorithm at a given rate to produce decoded data; an output buffer for buffering the block of decoded data; means for responding to a start-output signal provided by a preceding decoder in the ring by causing the buffered decoded data to be provided onto the data output bus at a predetermined rate that is greater than the given rate at which the coded data is processed to produce the decoded data; and means for providing a start-output signal to the succeeding decoder in the ring to cause the succeeding decoder to provide a portion of the buffered decoded data therein onto the data output bus at a predetermined rate and at such time as to be continuous from and not overlap the portion of the buffered decoded data provided onto the output data bus from the instant said decoder.
Claim 2
Dependent Claim
317 words
A decoding system capable of outputting Viterbi-decoding-algorithmdecoded data at a predetermined rate that is greater than a given rate at which coded data is processed in accordance with said algorithm by a single decoder to produce the decoded data, comprising a data input bus; a data output bus; a ring of decoders, with each decoder coupled to the input bus for receiving coded data from the input bus and coupled to the output bus for providing decoded data onto the output bus; wherein each said decoder includes an input buffer for responding to a start-input signal from a preceding decoder in the ring by buffering a block of the received coded data; means for providing a start-input signal to a succeeding decoder in the ring at such time as to cause the succeeding decoder to receive a block of coded data from the input bus that overlaps the block of coded data received from the input bus by the instant said decoder; processing means for processing the buffered block of coded data in accordance with a Viterbi decoding algorithm at a given rate to produce decoded data; an output buffer for buffering the block of decoded data; means for responding to a start-output signal provided by a preceding decoder in the ring by causing the buffered decoded data to be provided onto the data output bus at a predetermined rate that is greater than the given rate at which the coded data is processed to produce the decoded data; and means for providing a start-output signal to the succeeding decoder in the ring to cause the succeeding decoder to provide a portion of the buffered decoded data therein onto the data output bus at a predetermined rate and at such time as to be continuous from and not overlap the portion of the buffered decoded data provided onto the output data bus from the instant said decoder.
Claim 3
Dependent Claim
123 words
A system according to claim 1, further comprising a synchronization-state bus; wherein each said decoder further comprises means for synchronizing the buffered coded data for processing by the processing means; and means for providing onto the synchronization-state bus during the provision of the decoded data onto the output data bus, synchronization-state information indicating the synchronization state of the buffered coded data for processing upon finishing the decoding of the block of coded data that is being provided onto the output data bus; wherein the synchronizing means initialize the synchronization state of the buffered coded data for processing by the processing means in accordance with the last synchronization-state information provided onto the synchronizationstate bus prior to beginning to process a block of coded data.
Claim 4
Dependent Claim
86 words
A system according to claim 2, wherein each said decoder further comprises means responsive to a predetermined mode signal for causing the synchronizing means to initialize the synchronization state of the buffered coded data for processing by the processing means prior to beginning to process a block of buffered coded data, in accordance with the synchronization-state information provided on the synchronization-state bus by a predetermined master said decoder instead of in accordance with the last synchronization-state information provided on the synchronization-state bus by some other decoder.
Claim 5
Dependent Claim
148 words
A system according to claim 2, wherein each said decoder further includes means for determining whether the buffered coded data is in a synchronization state that enables the coded data to be correctly decoded by the processing means; wherein the synchronizing means includes means for resynchronizing the buffered coded data for processing by the processing means when it is determined that the buffered coded data is not in a synchronization state that enables the buffered coded data to be correctly decoded by the processing means; and wherein the system further comprises means for detecting a perturbation in the coded data received on the data input bus; means for providing a sync-hold signal for a predetermined duration in response to detecting a said perturbation; and means for reponding to said sync-hold signal by inhibiting the synchronizing means from resynchronizing said coded data during the duration of said sync-hold signal.
Claim 6
Dependent Claim
48 words
A system according to claim 4, further comprising means for inhibiting the synchronizing means from resynchronizing said coded data following the duration of the sync-hold signal until such time as a new block of coded data is buffered into the first buffering means of the first said decoder.
Claim 7
Dependent Claim
94 words
A system according to claim 1, further comprising an activity-state bus; wherein each said decoder includes means for providing an activity indication signal on the activity-state bus while decoded data is being provided onto the data output bus from the instant said decoder; and wherein at least one said decoder includes means for monitoring the activity-state bus; and means for ceasing operation of the instant said decoder if there is already an activity indication signal on the activity-state bus when the instant said decoder begins to provide decoded data onto the data output bus.
Claim 8
Dependent Claim
105 words
A system according to claim 6, further comprising a system controller for monitoring the status of the activity-state bus and for providing a reset signal to the decoders when said monitoring does not detect that decoded data is being provided onto the output bus from the decoders in the ring; wherein at least one of the decoders in the ring is responsive to said reset signal, in lieu of said start-input signal and in lieu of said start-output signal, for inputting a block of coded data into the input buffer and for causing buffered decoded data to be provided onto the data output bus respectively.
Claim 9
Dependent Claim
44 words
A system according to claim 1, wherein each said decoder further includes means for ceasing operation of the instant said decoder if a start-input signal is received by the instant said decoder while the processing means thereof is processing said block of coded data.
Claim 10
Dependent Claim
146 words
A system according to claim 8, further comprising an activity-state bus; wherein each said decoder includes means for providing an activity indication signal on the activity-state bus while decoded data is being provided onto the data output bus from the instant said decoder; and wherein the system further comprises a system controller for monitoring the status of the activity-state bus and for providing a reset signal to the decoders when said monitoring does not detect that decoded data is being provided onto the output bus from the decoders in the ring; wherein at least one of the decoders in the ring is responsive to said reset signal, in lieu of said start-input signal and in lieu of said start-output signal, for inputting a block of coded data into the input buffer and for causing buffered decoded data to be provided onto the data output bus respectively.
Claim 11
Dependent Claim
44 words
A system according to claim 1, wherein each said decoder further includes means for ceasing operation of the instant said decoder if a start-output signal is received by the instant said decoder while the processing means thereof is processing said block of coded data.
Claim 12
Dependent Claim
146 words
A system according to claim 10, further comprising an activity-state bus; wherein each said decoder includes means for providing an activity indication signal on the activity-state bus while decoded data is being provided onto the data output bus from the instant said decoder; and wherein the system further comprises a system controller for monitoring the status of the activity-state bus and for providing a reset signal to the decoders when said monitoring does not detect that decoded data is being provided onto the output bus from the decoders in the ring; wherein at least one of the decoders in the ring is responsive to said reset signal, in lieu of said start-input signal and in lieu of said start-output signal, for inputting a block of coded data into the input buffer and for causing buffered decoded data to be provided onto the data output bus respectively.
Claim 13
Dependent Claim
306 words
A decoding system capable of outputting decoded data at a predetermined rate that is greater than a given rate at which coded data is processed by a single decoder to produce the decoded data, comprising a data input bus; a data output bus; a ring of decoders, with each decoder being coupled to the input bus for receiving coded data from the input bus and coupled to the output bus for providing decoded data onto the output bus; wherein each said decoder includes an input buffer for responding to a start-input signal from a preceding decoder in the ring by buffering a block of the received coded data; means for providing a start-input signal to a succeeding decoder in the ring at such time as to cause the succeeding decoder to receive a block of coded data from the input bus that overlaps the block of coded data received from the input bus by the instant said decoder; processing means for processing the buffered block of coded data at a given rate to produce decoded data; an output buffer for buffering the block of decoded data; means for responding to a start-output signal provided by a preceding decoder in the ring by causing the buffered decoded data to be provided onto the data output bus at a predetermined rate that is greater than the given rate at which the coded data is processed to produce the decoded data; and means for providing a start-output signal to the succeeding decoder in the ring to cause the succeeding decoder to provide a portion of the buffered decoded data therein onto the data output bus at a predetermined rate and at such time as to be continuous from and not overlap the portion of the buffered decoded data provided onto the output data bus from the instant said decoder.
Claim 14
Dependent Claim
306 words
A decoding system capable of outputting decoded data at a predetermined rate that is greater than a given rate at which coded data is processed by a single decoder to produce the decoded data, comprising a data input bus; a data output bus; a ring of decoders, with each decoder being coupled to the input bus for receiving coded data from the input bus and coupled to the output bus for providing decoded data onto the output bus; wherein each said decoder includes an input buffer for responding to a start-input signal from a preceding decoder in the ring by buffering a block of the received coded data; means for providing a start-input signal to a succeeding decoder in the ring at such time as to cause the succeeding decoder to receive a block of coded data from the input bus that overlaps the block of coded data received from the input bus by the instant said decoder; processing means for processing the buffered block of coded data at a given rate to produce decoded data; an output buffer for buffering the block of decoded data; means for responding to a start-output signal provided by a preceding decoder in the ring by causing the buffered decoded data to be provided onto the data output bus at a predetermined rate that is greater than the given rate at which the coded data is processed to produce the decoded data; and means for providing a start-output signal to the succeeding decoder in the ring to cause the succeeding decoder to provide a portion of the buffered decoded data therein onto the data output bus at a predetermined rate and at such time as to be continuous from and not overlap the portion of the buffered decoded data provided onto the output data bus from the instant said decoder.
Claim 15
Dependent Claim
120 words
A system according to claim 12, further comprising a synchronization-state bus; wherein each said decoder further comprises means for synchronizing the coded data for processing by the processing means; and means for providing onto the synchronization-state bus during the provision of the decoded data onto the output data bus, synchronization-state information indicating the synchronization state of the coded data for processing upon finishing the decoding of the block of coded data that is being provided onto the output data bus; wherein the synchronizing means initialize the synchronization state of the coded data for processing by the processing means in accordance with the last synchronization-state information provided onto the synchronization-state bus prior to beginning to process a block of coded data.
Claim 16
Dependent Claim
85 words
A system according to claim 13, wherein each said decoder further comprises means responsive to a predetermined mode signal for causing the synchronizing means to initialize the synchronization state of the coded data for processing by the processing means prior to beginning to process a block of coded data, in accordance with the synchronization-state information provided on the synchronization-state bus by a predetermined master said decoder instead of in accordance with the last synchronization-state information provided on the synchronization-state bus by some other said decoder.
Claim 17
Dependent Claim
144 words
A system according to claim 13, wherein each said decoder further includes means for determining whether the coded data is in a synchronization state that enables the coded data to be correctly decoded by the processing means; wherein the synchronizing means includes means for resynchronizing the coded data for processing by the processing means when it is determined that the coded data is not in a synchronization state that enables the coded data to be correctly decoded by the processing means; and wherein the system further comprises means for detecting a perturbation in the coded data received on the data input bus; means for providing a sync-hold signal for a predetermined duration in response to detecting a said perturbation; and means for responding to said sync-hold signal by inhibiting the synchronizing means from resynchronizing said coded data during the duration of said sync-hold signal.
Claim 18
Dependent Claim
48 words
A system according to claim 15, further comprising means for inhibiting the synchronizing means from resynchronizing said coded data following the duration of the sync-hold signal until such time as a new block of coded data is buffered into the first buffering means of the first said decoder.
Claim 19
Dependent Claim
94 words
A system according to claim 12, further comprising an activity-state bus; wherein each said decoder includes means for providing an activity indication signal on the activity-state bus while decoded data is being provided onto the data output bus from the instant said decoder; and wherein at least one said decoder includes means for monitoring the activity-state bus; and means for ceasing operation of the instant said decoder if there is already an activity indication signal on the activity-state bus when the instant said decoder begins to provide decoded data onto the data output bus.
Claim 20
Dependent Claim
105 words
A system according to claim 17, further comprising a system controller for monitoring the status of the activity-state bus and for providing a reset signal to the decoders when said monitoring does not detect that decoded data is being provided onto the output bus from the decoders in the ring; wherein at least one of the decoders in the ring is responsive to said reset signal, in lieu of said start-input signal and in lieu of said start-output signal, for inputting a block of coded data into the input buffer and for causing buffered decoded data to be provided onto the data output bus respectively.
Claim 21
Dependent Claim
44 words
A system according to claim 12, wherein each said decoder further includes means for ceasing operation of the instant said decoder if a start-input signal is received by the instant said decoder while the processing means thereof is processing said block of coded data.
Claim 22
Dependent Claim
146 words
A system according to claim 19, further comprising an activity-state bus; wherein each said decoder includes means for providing an activity indication signal on the activity-state bus while decoded data is being provided onto the data output bus from the instant said decoder; and wherein the system further comprises a system controller for monitoring the status of the activity-state bus and for providing a reset signal to the decoders when said monitoring does not detect that decoded data is being provided onto the output bus from the decoders in the ring; wherein at least one of the decoders in the ring is responsive to said reset signal, in lieu of said start-input signal and in lieu of said start-output signal, for inputting a block of coded data into the input buffer and for causing buffered decoded data to be provided onto the data output bus respectively.
Claim 23
Dependent Claim
44 words
A system according to claim 12, wherein each said decoder further includes means for ceasing operation of the instant said decoder if a start-output signal is received by the instant said decoder while the processing means thereof is processing said block of coded data.
Claim 24
Dependent Claim
146 words
A system according to claim 21, further comprising an activity-state bus; wherein each said decoder includes means for providing an activity indication signal on the activity-state bus while decoded data is being provided onto the data output bus from the instant said decoder; and wherein the system further comprises a system controller for monitoring the status of the activity-state bus and for providing a reset signal to the decoders when said monitoring does not detect that decoded data is being provided onto the output bus from the decoders in the ring; wherein at least one of the decoders in the ring is responsive to said reset signal, in lieu of said start-input signal and in lieu of said start-output signal, for inputting a block of coded data into the input buffer and for causing buffered decoded data to be provided onto the data output bus respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-06 | 1993-05-08 | 1993-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-06 | 1997-05-08 | 1997-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-06 | 2001-05-08 | 2001-11-07 | $7700.00 | Window Closed / Lapsed |