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US4879684A
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Write-read circuit
Assignee: Jenoptik AG
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Filing: 1988-03-16
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Granted: 1989-11-07
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Expires: 2008-03-16
Abstract
Abstract A read-write circuit has two data lines each of which is associated with a read circuit. The read circuit consists of three transistors connected in series, which operate in the low-signal mode in reading. By taking current from or into the bit lines according to the previously stored information the voltage ratios are changed at the outputs by which a data output driver is controlled. In writing, the n-transistors in the read circuits form with two p-transistors NOT circuits whose outputs form the data lines.
Inventors
- 👤 Mathias Krauss
- 👤 Horst-Guenter Schniek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:35
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/06; G11C7/062; G11C7/1078; G11C7/1096
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
226 words
In a read-write circuit for a CMOS memory connected to the read-write circuit via first and second data memory lines and two selector transistors, the memory being controlled by a bit line decoder and having one pair of bit lines each connected to a sensor flip-flop, the read-write circuit being furthermore connected by first and second data input lines to a data input buffer and being connected by first and second data output lines to a data output driver, the read-write circuit including first and second read circuits associated with said first and second data memory lines, respectively, the improvement wherein the first and second data input lines are connected by first and second transfer gates to the inputs of first and second inverters and via first and second n-transistors, respectively, to the gates of third and fourth low-resistance n-transistors in the second and first read circuits, respectively, first and second low-resistance p-transistors being connected to the outputs of the first and second inverters, respectively, for connecting a supply voltage to the first and second data memory lines, respectively, and wherein fifth and sixth n-transistors are connected between the inputs of the first and second inverters and a ground reference, and further comprising means for rendering said first and second transfer gates conductive and rendering said fifth and sixth n-transistors non-conductive during writing to said memory.
Claim 2
Dependent Claim
226 words
In a read-write circuit for a CMOS memory connected to the read-write circuit via first and second data memory lines and two selector transistors, the memory being controlled by a bit line decoder and having one pair of bit lines each connected to a sensor flip-flop, the read-write circuit being furthermore connected by first and second data input lines to a data input buffer and being connected by first and second data output lines to a data output driver, the read-write circuit including first and second read circuits associated with said first and second data memory lines, respectively, the improvement wherein the first and second data input lines are connected by first and second transfer gates to the inputs of first and second inverters and via first and second n-transistors, respectively, to the gates of third and fourth low-resistance n-transistors in the second and first read circuits, respectively, first and second low-resistance p-transistors being connected to the outputs of the first and second inverters, respectively, for connecting a supply voltage to the first and second data memory lines, respectively, and wherein fifth and sixth n-transistors are connected between the inputs of the first and second inverters and a ground reference, and further comprising means for rendering said first and second transfer gates conductive and rendering said fifth and sixth n-transistors non-conductive during writing to said memory.
Claim 3
Dependent Claim
46 words
The read-write circuit of claim 1, wherein third and fourth high-resistance p-transistors are connected between the supply voltage and the gates of the third and fourth n-transistors, the outputs of the first and second inverters being connected to the gates of the third and fourth p-transistors.
Claim 4
Dependent Claim
143 words
The read-write circuit of claim 1, wherein third and fourth high resistance p-transistors are connected in the first and second read circuits between the supply voltage and first and second functions, respectively, seventh and eighth low-resistance n-transistors are connected between the first and second junctions and the first and second data memory lines, said seventh and eighth n-transistors being controlled by a cycled reference voltage, and the fourth and third low-resistance n-transistors are connected between the first and second data memory lines and ground, and wherein ninth and tenth n-transistors connected to be non-conductive when writing to the memory connect the first and second data lines to the gates of the fourth and third n-transistors, and third and fourth transfer transistors connected to be conductive when reading from the memory connect the first and second junctions to the first and second output lines.
Claim 5
Dependent Claim
24 words
The read-write circuit of claim 3, wherein the gates of the third and fourth p-transistors are connected to the second and first data lines.
Claim 6
Dependent Claim
27 words
The read-write circuit of claim 1, wherein an n-transistor controlled by a reference voltage is connected between the supply voltage and one of the data memory lines.
References Cited (Backward Citations)
US4575823A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-06 | 1993-05-08 | 1993-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-06 | 1997-05-08 | 1997-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-06 | 2001-05-08 | 2001-11-07 | $7700.00 | Window Closed / Lapsed |