US4879674A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input circuit for a digital phase locked loop
Assignee: Yamaha Corp
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Filing: 1988-01-14
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Granted: 1989-11-07
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Expires: 2008-01-14
Abstract
Abstract For reliable and stable detection of the movement of a mobile body, a pair of filters for performing specified and different calculations are interposed between an analog-digital (A/D) converter and a digital phase locked circuit. The calculations carried out by the filters are selectively utilized either alone or in combination to minimize noise present after A/D conversion.
Inventors
- 👤 Kenzaburou Iijima
- 👤 Yoshinori Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:52
CPC Classifications
H; H03; H03H; H03H15/00; H03M; H03M1/00; H03M1/06; H03M1/08; H03M13/00
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
189 words
An input circuit for a digital phase locked loop circuit, the input circuit comprising; an A/D converter having means to receive an input signal; a first filter coupled to said A/D converter and performing a first calculation (D k-1 +1) when D k is larger than D k-1 , a second calculation (D k-1 -1) when D k is smaller than D k-1 , and a third calculation (D k-1 ) when D k is equal to D k-1 , wherein D k and D k-1 are current and one-time previous values of a first output signal from said A/D converter; a second filter coupled to said A/D converter via said first filter and performing a fourth calculation (2·D t +D t-1 +D t-2 )/4, wherein D t , D t-1 and D t-2 are current, one-time previous and two-times previous values of a second output signal from said A/D converter; and means for selectively transferring a signal to the digital phase locked circuit after either said calculation by said first filter, after said calculation by second filter, or after said calculations by both said first and second filters.
Claim 2
Dependent Claim
189 words
An input circuit for a digital phase locked loop circuit, the input circuit comprising; an A/D converter having means to receive an input signal; a first filter coupled to said A/D converter and performing a first calculation (D k-1 +1) when D k is larger than D k-1 , a second calculation (D k-1 -1) when D k is smaller than D k-1 , and a third calculation (D k-1 ) when D k is equal to D k-1 , wherein D k and D k-1 are current and one-time previous values of a first output signal from said A/D converter; a second filter coupled to said A/D converter via said first filter and performing a fourth calculation (2·D t +D t-1 +D t-2 )/4, wherein D t , D t-1 and D t-2 are current, one-time previous and two-times previous values of a second output signal from said A/D converter; and means for selectively transferring a signal to the digital phase locked circuit after either said calculation by said first filter, after said calculation by second filter, or after said calculations by both said first and second filters.
Claim 3
Dependent Claim
36 words
An input circuit as claimed in claim 1, further comprising a sampling period switch coupled to said A/D converter for adjusting the sampling period of the A/D converter depending on the frequency of an input signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-06 | 1993-05-08 | 1993-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-06 | 1997-05-08 | 1997-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-06 | 2001-05-08 | 2001-11-07 | $7700.00 | Window Closed / Lapsed |