Patent US4879254A successfully refreshed from Google Patents.
US4879254A
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US
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Method of manufacturing a DMOS
Assignee: Denso Corp
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Filing: 1988-06-09
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Granted: 1989-11-07
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Expires: 2008-06-09
Abstract
Abstract A method for manufacturing a DMOS which comprises forming a first conductive type layer on a substrate, forming a gate oxide layer thereon, forming a gate electrode layer and a second insulating layer successively on the gate oxide layer, forming a second conductive type body region and a first conductive type source region having a narrower width by implanting impurities utilizing the second insulating layer as a mask, forming a side wall spacer of an insulating material on at least a side portion of the gate electrode, forming a conductive passage penetrating the source region and extending into the body region while utilizing the second insulating layer and the side wall spacer as mask, optionally implanting the exposed body region, further excessively etching the sidewall spacer, the masking layer overlying the gate, and the gate oxide prior to providing an electrode connecting the source and body regions.
Inventors
- 👤 Yukio Tsuzuki
- 👤 Masami Yamaoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:17
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D62/00; H10D62/10; H10D62/17; H10D62/393; H10D62/80; H10D62/83; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/252; H10D64/2527; H10D64/256; H10D64/60; H10D64/62; Y; Y10; Y10S; Y10S148/00; Y10S148/103; Y10S148/111; Y10S148/126; Y10S148/131
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
230 words
A method of manufacturing a semiconductor device, which comprises the steps of: forming a first conductivity-type layer, having a low impurity atom concentration, on one main surface of a substrate; forming a first insulating layer on one main surface of said first conductivity-type layer followed by forming a gate electrode layer and a second insulating layer successively on a region of said first insulating layer; forming, in said first conductivity-type layer, both a second conductivity-type region and a first conductivity-type region having a narrower width than that of said second conductivity-type region by doping impurities into said first conductivity-type layer utilizing said second insulating layer as a mask: forming a side wall of an insulating material on at least a side portion of said gate electrode layer; forming a conductive portion penetrating through said first conductivity-type region and extending into said second-conductivity-type region utilizing said second insulating layer and said insulating material on said side wall as a mask; excessively etching said insulating material on said side wall, said first insulating layer, and said second insulating layer to widen an area defined by said side wall; forming a first electrode electrically connected to said first conductivity-type region and said second-conductivity-type region through said conductive portion on a main surface of said first conductivity-type layer; and forming a second electrode on an opposite side of a main surface of said substrate.
Claim 2
Independent Claim
230 words
A method of manufacturing a semiconductor device, which comprises the steps of: forming a first conductivity-type layer, having a low impurity atom concentration, on one main surface of a substrate; forming a first insulating layer on one main surface of said first conductivity-type layer followed by forming a gate electrode layer and a second insulating layer successively on a region of said first insulating layer; forming, in said first conductivity-type layer, both a second conductivity-type region and a first conductivity-type region having a narrower width than that of said second conductivity-type region by doping impurities into said first conductivity-type layer utilizing said second insulating layer as a mask: forming a side wall of an insulating material on at least a side portion of said gate electrode layer; forming a conductive portion penetrating through said first conductivity-type region and extending into said second-conductivity-type region utilizing said second insulating layer and said insulating material on said side wall as a mask; excessively etching said insulating material on said side wall, said first insulating layer, and said second insulating layer to widen an area defined by said side wall; forming a first electrode electrically connected to said first conductivity-type region and said second-conductivity-type region through said conductive portion on a main surface of said first conductivity-type layer; and forming a second electrode on an opposite side of a main surface of said substrate.
Claim 3
Dependent Claim
92 words
A method of manufacturing a semiconductor device according to claim 1, wherein said forming a conductive portion step includes the steps of forming a metallic compound by first forming a metallic layer on a surface of said first conductivity-type region while utilizing said second insulating layer and said side wall as a mask, and then heating said metallic layer to reduce same to said metallic compound in a region of said first conductivity type region, and the top end portion thereof to reach said second conductivity-type region through said first conductivity-type region.
Claim 4
Dependent Claim
29 words
A method of manufacturing a semiconductor device according to claim 1, wherein said first insulating layer is an N + type diffusion region containing As therein as the impurity.
Claim 5
Dependent Claim
36 words
A method of manufacturing a semiconductor device according to claim 1, wherein said insulating material for forming at least said side wall is Tetraethoxysilane (TEOS) and said insulating layer is formed by a TEOS CVD method.
Claim 6
Dependent Claim
37 words
A method for manufacturing a semiconductor device according to claim 1, wherein said conductive portion is a concave portion formed by an etching method while utilizing said second insulating layer and said side wall as a mask.
Claim 7
Dependent Claim
42 words
A method for manufacturing a semiconductor device according to claim 1, wherein said conductive portion consists of a second conductivity type diffusing region formed by an ion implantation method while utilizing said second insulating layer and said side wall as a mask.
Claim 8
Dependent Claim
29 words
A method for manufacturing a semiconductor device according to claim 2, wherein a metallic substance of said metallic layer is the same material as that of the first electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-06 | 1993-05-08 | 1993-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-06 | 1997-05-08 | 1997-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-06 | 2001-05-08 | 2001-11-07 | $7700.00 | Window Closed / Lapsed |