US4878181A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video display controller for expanding monochrome data to programmable foreground and background color image data
Assignee: Signetics Corp
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Filing: 1987-11-13
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Granted: 1989-10-31
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Expires: 2007-11-13
Abstract
Abstract A circuit which expands monochrome character image patterns to color form for use in a raster scanned computer display system. Monochrome patterns are expanded from one bit per pixel to n bits per pixel. Foreground and background colors are programmable in a pattern generator which uses data from the expanded source patterns to select appropriate colors and characters for a destination pattern to be displayed. The expanded multicolor image is generated by hardware.
Inventors
- 👤 Craig A. MacKenna
- 👤 Jan-Kwei J. Li
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:44
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/02; G09G5/024
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
454 words
A video display controller for use in a color image display system for expanding a monochrome image pattern stored in a display memory in the form of one bit per image pixel to a color image pattern having multiple bits signifying foreground and background color of each pixel, and integrating such multiple bits with the stored bit pattern to derive a corresponding color image; such video controller comprising: a bit expander circuit including a source latch for storing the pixel bits of a part of said monochrome image; bits per pixel means for setting the number of bits per pixel in the expanded color image of said part of said monochrome image, to thereby define the extent of the multiple bit expansion to be performed; source tracking means which monitor the contents of said source latch and signal when to reload said source latch from said display memory; and expansion logic circuit means having inputs connected to outputs of said source latch, said bits per pixel means, and said source tracking means; said expansion logic circuit means having outputs at which it produces signals respectively representing the contents of said source latch and a number of consecutive bits corresponding to an expansion of the contents of said source latch, the number of consecutive bits in such expansion which correspond to each bit in the source latch being as defined by said bits per pixel means; pattern alignment means for shifting the signals at the outputs of said expansion logic circuit means so as to correspond to the positioning of destination words stored in said display memory; pattern generating circuit means including a foreground color register programmable with pixel values to be substituted for "1" pixel bits of said monochrome image; a background color register programmable with pixel values which are to be substituted for "0" pixel bits of said monochrome image; a single-bit register programmable to control whether "0" pixel bits in said monochrome image pattern are to remain unchanged or are to be replaced by pixel values stored in said background color register; a destination latch for temporarily storing destination words stored in said display memory; and multiplexing means which selects among the contents of said foreground color register, said background color register and said destination latch under control of said single-bit register and said pattern alignment means; said multiplexing means having an output at which it produces new destination words for replacing destination words currently stored in said display memory; and control means which sequence the reading of said display memory and storage of data therefrom in said source latch and in said destination latch, and the writing of said new destination words provided by said multiplexing means into said display memory.
Claim 2
Dependent Claim
454 words
A video display controller for use in a color image display system for expanding a monochrome image pattern stored in a display memory in the form of one bit per image pixel to a color image pattern having multiple bits signifying foreground and background color of each pixel, and integrating such multiple bits with the stored bit pattern to derive a corresponding color image; such video controller comprising: a bit expander circuit including a source latch for storing the pixel bits of a part of said monochrome image; bits per pixel means for setting the number of bits per pixel in the expanded color image of said part of said monochrome image, to thereby define the extent of the multiple bit expansion to be performed; source tracking means which monitor the contents of said source latch and signal when to reload said source latch from said display memory; and expansion logic circuit means having inputs connected to outputs of said source latch, said bits per pixel means, and said source tracking means; said expansion logic circuit means having outputs at which it produces signals respectively representing the contents of said source latch and a number of consecutive bits corresponding to an expansion of the contents of said source latch, the number of consecutive bits in such expansion which correspond to each bit in the source latch being as defined by said bits per pixel means; pattern alignment means for shifting the signals at the outputs of said expansion logic circuit means so as to correspond to the positioning of destination words stored in said display memory; pattern generating circuit means including a foreground color register programmable with pixel values to be substituted for "1" pixel bits of said monochrome image; a background color register programmable with pixel values which are to be substituted for "0" pixel bits of said monochrome image; a single-bit register programmable to control whether "0" pixel bits in said monochrome image pattern are to remain unchanged or are to be replaced by pixel values stored in said background color register; a destination latch for temporarily storing destination words stored in said display memory; and multiplexing means which selects among the contents of said foreground color register, said background color register and said destination latch under control of said single-bit register and said pattern alignment means; said multiplexing means having an output at which it produces new destination words for replacing destination words currently stored in said display memory; and control means which sequence the reading of said display memory and storage of data therefrom in said source latch and in said destination latch, and the writing of said new destination words provided by said multiplexing means into said display memory.
Claim 3
Dependent Claim
41 words
A video display controller as claimed in claim 1, wherein said bits per pixel means is programmable to set the number of bits per pixel in the monochrome image at any of 1, 2, 4, or 8 bits per such pixel.
Claim 4
Dependent Claim
19 words
A video display controller as claimed in claim 1, wherein said bits per pixel means is a programmable register.
Claim 5
Dependent Claim
86 words
A video display controller as claimed in any of claims 1, 2 or 3, wherein said source tracking means comprises: a counter capable of counting from zero through the number of bits per pixel minus 1; and a multiplexer having data inputs at which it receives the outputs of said counter and control inputs at which it receives the outputs of said bits per pixel means; said multiplexer having an output at which it produces a signal indicating when said source latch is to be reloaded.
Claim 6
Dependent Claim
27 words
A video display controller as claimed in any of claims 1, 2 or 3, wherein said expansion logic circuit means is a programmable logic array (PLA) structure.
Claim 7
Dependent Claim
389 words
In a raster scan video display controller of a computer controlled video display system, a logic circuit for expanding source pattern data of a monochrome image stored in a display memory of the system into destination pattern data of an expanded color image to be displayed, such logic circuit comprising: an image update control unit for fetching source pattern data from said display memory; an expander circuit comprising: a programmable bit per pixel register for setting the number of bits in the displayed color image corresponding to each bit in said source pattern; a counter for controlling the sequence of expanded bits corresponding to each bit in said source pattern; a source pattern latch which sequentially receives monochrome source pattern data from said control unit; a programmable logic array (PLA) having as inputs the contents of said source pattern latch, said bits per pixel register, and said counter; the output of said PLA being a sequence of expanded destination pattern data corresponding to said source pattern data; and a source completion multiplexer connected to said counter and to said bits per pixel register and producing an output signal indicating completion of the expansion of the source pattern data in said source pattern latch, such signal causing said control unit to fetch the next source pattern from said display memory for storage in said source pattern latch, such signal being produced when the output of said counter has a value corresponding to the number of bits per pixel set by said bits per pixel register; a pattern generator comprising: a foreground color latch programmable with a color code for the foreground color of the displayed image; a background color latch programmable with a color code for the background color of the displayed image; a destination latch which sequentially receives from said display memory destination pattern data corresponding to pixels of the displayed image; a write/overlay register programmable to indicate whether the background of the displayed image is to be colored; a background multiplexer for selecting between data in said destination latch and data in said background color latch under the control of said write/overlay register; and means controlled by said expanded destination data produced by said PLA to select between data from said foreground color latch and from said background multiplexer, such selected data representing the color expanded displayed image.
Claim 8
Dependent Claim
389 words
In a raster scan video display controller of a computer controlled video display system, a logic circuit for expanding source pattern data of a monochrome image stored in a display memory of the system into destination pattern data of an expanded color image to be displayed, such logic circuit comprising: an image update control unit for fetching source pattern data from said display memory; an expander circuit comprising: a programmable bit per pixel register for setting the number of bits in the displayed color image corresponding to each bit in said source pattern; a counter for controlling the sequence of expanded bits corresponding to each bit in said source pattern; a source pattern latch which sequentially receives monochrome source pattern data from said control unit; a programmable logic array (PLA) having as inputs the contents of said source pattern latch, said bits per pixel register, and said counter; the output of said PLA being a sequence of expanded destination pattern data corresponding to said source pattern data; and a source completion multiplexer connected to said counter and to said bits per pixel register and producing an output signal indicating completion of the expansion of the source pattern data in said source pattern latch, such signal causing said control unit to fetch the next source pattern from said display memory for storage in said source pattern latch, such signal being produced when the output of said counter has a value corresponding to the number of bits per pixel set by said bits per pixel register; a pattern generator comprising: a foreground color latch programmable with a color code for the foreground color of the displayed image; a background color latch programmable with a color code for the background color of the displayed image; a destination latch which sequentially receives from said display memory destination pattern data corresponding to pixels of the displayed image; a write/overlay register programmable to indicate whether the background of the displayed image is to be colored; a background multiplexer for selecting between data in said destination latch and data in said background color latch under the control of said write/overlay register; and means controlled by said expanded destination data produced by said PLA to select between data from said foreground color latch and from said background multiplexer, such selected data representing the color expanded displayed image.
Claim 9
Dependent Claim
45 words
A logic circuit as claimed in claim 6, wherein said bits per pixel register is programmable to set the number of bits per pixel in the color expanded displayed image at any of one, two, four or eight bits per pixel in the monochrome image.
Claim 10
Dependent Claim
36 words
A logic circuit as claimed in claim 6, wherein a "0" bit in the monochrome source pattern is expanded to a series of bits in accordance with said second color code programmed into said background latch.
Claim 11
Dependent Claim
20 words
A logic circuit as claimed in claim 6, wherein a "0" bit in the monochrome source pattern is left unchanged.
Claim 12
Dependent Claim
21 words
A logic circuit as claimed in claim 6, wherein said monochrome source pattern is a character font in the monochrome image.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-30 | 1993-05-01 | 1993-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-30 | 1997-05-01 | 1997-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-30 | 2001-05-01 | 2001-10-31 | $7700.00 | Window Closed / Lapsed |