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US4878065A Expired / Lapsed US ⏱️ 0.0 years remaining

Thermal printing control circuit

Assignee: SUSUMU Co Ltd 14 UMAMAWASHI-CHO
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Filing: 1988-08-26
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Granted: 1989-10-31
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Expires: 2008-08-26
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Abstract

Abstract A thermal printing control circuit includes a first shift register for receiving and storing a series of serial printing image data to be printed by a plurality of thermal print elements, a second register, constituted by a plurality of registers for storing contents of the first shift register by parallelly and sequentially shifting and receiving the contents thereof, for storing printing history data of a plurality of cycles of the thermal print elements, and a logic circuit for performing a logic operation by using the printing history data of the plurality of cycles of the plurality of thermal print elements, the printing history data being stored in the second shift register, and externally supplied control timing signals and for generating drive signals representing voltage waveforms to be applied to the plurality of thermal print elements.

Inventors

  • 👤 Itaru Fukushima
  • 👤 Takashi Okamoto
  • 👤 Hisashi Deguchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 18:25
CPC Classifications
B; B41; B41J; B41J2/00; B41J2/315; B41J2/32; B41J2/35; B41J2/355; B41J2/3555

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 202 words
A thermal printing control circuit comprising: a first serial/parallel shift register for receiving serial image data to be serially printed and for temporarily storing the serial image data; a second parallel register group comprising a plurality of stages for storing image data corresponding to several previous print lines; a thermal head having heating elements corresponding to bits of printing data which are to be printed and are stored in a first stage of said second register group; a first logic gate group for calculating logic formulas t 0 , t A , t B , t C and t D by using a plurality of sequentially input fundamental timing signals (T 0 , T A , T B , T C , T D ) for balancing heat energy of the heating elements of said thermal head in accordance with the printing data of the previous several lines stored in said second register group, and the printing data to be printed; and a second logic gate group for calculating T=t 0 +t A +t B +t C +t D , the logic formulas t 0 , t A , t B , t C , and t D being defined by: ##EQU14##
Claim 2
Dependent Claim 202 words
A thermal printing control circuit comprising: a first serial/parallel shift register for receiving serial image data to be serially printed and for temporarily storing the serial image data; a second parallel register group comprising a plurality of stages for storing image data corresponding to several previous print lines; a thermal head having heating elements corresponding to bits of printing data which are to be printed and are stored in a first stage of said second register group; a first logic gate group for calculating logic formulas t 0 , t A , t B , t C and t D by using a plurality of sequentially input fundamental timing signals (T 0 , T A , T B , T C , T D ) for balancing heat energy of the heating elements of said thermal head in accordance with the printing data of the previous several lines stored in said second register group, and the printing data to be printed; and a second logic gate group for calculating T=t 0 +t A +t B +t C +t D , the logic formulas t 0 , t A , t B , t C , and t D being defined by: ##EQU14##
Claim 3
Dependent Claim 29 words
A thermal printing control circuit comprising a plurality of thermal printing control circuits of claim 1, and a connecting circuit for interconnecting said plurality of thermal printing control circuits.
Claim 4
Dependent Claim 208 words
A thermal printing control circuit comprising: a plurality of integrated circuits each of which can control N thermal print elements; and connecting means for connecting said plurality of integrated circuits to each other; said integrated circuit including: a (N+M)-bit first shift register for receiving and storing a series of serial printing image data to be printed by said N thermal print elements, where M is larger than one; a second register, constituted by a plurality of (N+M)-bit registers for storing contents of said first shift register by parallelly and sequentially shifting and receiving the contents thereof, for storing printing history data of a plurality of cycles of said N thermal print elements; and a logic circuit for performing a logic operation by using the printing history data of the plurality of cycles of said N thermal print elements, the printing history data being stored in said second shift register, and externally supplied control timing data and for generating drive signals representing voltage waveforms to be applied to said N thermal print elements in a current cycle, wherein said connecting means connects an input terminal of said first shift register of one of said integrated circuit to intermediate bit outputs of said first shift registers of other integrated circuits.
Claim 5
Dependent Claim 208 words
A thermal printing control circuit comprising: a plurality of integrated circuits each of which can control N thermal print elements; and connecting means for connecting said plurality of integrated circuits to each other; said integrated circuit including: a (N+M)-bit first shift register for receiving and storing a series of serial printing image data to be printed by said N thermal print elements, where M is larger than one; a second register, constituted by a plurality of (N+M)-bit registers for storing contents of said first shift register by parallelly and sequentially shifting and receiving the contents thereof, for storing printing history data of a plurality of cycles of said N thermal print elements; and a logic circuit for performing a logic operation by using the printing history data of the plurality of cycles of said N thermal print elements, the printing history data being stored in said second shift register, and externally supplied control timing data and for generating drive signals representing voltage waveforms to be applied to said N thermal print elements in a current cycle, wherein said connecting means connects an input terminal of said first shift register of one of said integrated circuit to intermediate bit outputs of said first shift registers of other integrated circuits.

References Cited (Backward Citations)

JPS59176070A Cited
US4567488A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-10-30 1993-05-01 1993-10-31 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-10-30 1997-05-01 1997-10-31 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-10-30 2001-05-01 2001-10-31 $7700.00 Window Closed / Lapsed

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