Method and apparatus for high accuracy measurment of VLSI components

Claim 2

A digital integrated circuit having an operational mode and a test mode, comprising: a plurality of digital circuits selected from combinatorial logic, latching circuitry and combinations thereof, each digital circuit having an operational signal path therethrough from an input to an output; control means for permitting measurement of propagation delay through said plurality of digital circuits with test equipment having an operational speed that is comparable to the operating speed of said plurality of digital circuits; said control means comprising intercoupling gate means and means connecting the gate means between separate digital circuits, said gate means being responsive to a test mode signal for individually coupling the outputs of selected ones of said plurality of digital circuits to the inputs of other selected ones of said plurality of digital circuits in series to define a test signal path comprising at least two operational signal paths connected in series so that a test signal applied to said integrated circuit in the test mode propagates through said test signal path; whereby the propagation delay through said test signal path is the sum of the individual propagation delays through each of the digital circuits in the test signal path, and is substantially longer than the propagation delay through any of said operation signal paths and can be accurately and directly measured with said test equipment without further processing.

Claim 3

A digital integrated circuit as defined in claim 1 wherein said gate means includes a logic gate having one input coupled to said test mode signal, another input coupled to the output of the previous digital circuit in said test signal path and an output coupled to the input of the next digital circuit in said test signal path.

Claim 4

A digital integrated circuit as defined in claim 1 wherein said digital circuits each include an input logic gate having an input for connection of the output from the previous digital circuit in said test signal path.

Claim 7

A delay measuring method as defined in claim 4 wherein the step of individually coupling the outputs of selected ones of said digital circuits to the inputs of other selected ones of said digital circuits in series includes the step of individually coupling digital circuits with similar delay characteristics in series.

Claim 8

A delay measuring method as defined in claim 4 wherein the step of individually coupling the outputs of selected ones of said digital circuits to the inputs of other selected ones of said digital circuits in series includes the step of individually coupling digital circuits with similar delay characteristics in series to define at least two test signal paths through said integrated circuit.

Claim 9

A delay measuring method as defined in claim 4 wherein the step of individually coupling the outputs of selected ones of said digital circuits to the inputs of other selected ones of said digital circuits in series includes selectively and individually coupling the outputs of different ones of said digital circuits to the inputs of other different ones of said digital circuits in series to define different test signal paths.

Claim 10

A delay measuring method as defined in claim 4 wherein the step of individually coupling the outputs of selected ones of said digital circuits to the inputs of other selected ones of said digital circuits in series is performed under control of a test mode signal when measurement of propagation delay is required.

Claim 11

A digital integrated circuit having an operation mode and a test mode comprising: a first plurality of digital circuits, each having an operational signal path therethrough from an input to an output; a second plurality of digital circuits, each having an operational signal path therethrough from an input to an output, said digital circuits each being selected from combinational logic, latching circuitry and combinations thereof; a first control means for permitting measurement of propagation delay through said first plurality of digital circuits with test equipment having an operating speed that is comparable to the operating speed of said digital circuits, said first control means comprising intercoupling gate means and means connecting the gate means between separate digital circuits, said gate means being responsive to a first test mode signal for individually coupling the outputs of selected ones of said first plurality of digital circuits to the inputs of other selected ones of said first plurality of digital circuits in series to define a first test signal path comprising at least two operational signal paths connected in series so that a first test signal applied to the input of said first test signal path in the test mode propagates through said first test signal path; a second control means for permitting measurement of propagation delay through said second plurality of digital circuits with said test equipment, said second control means comprising intercoupling means responsive to a second test mode signal for individually coupling the outputs of selected ones of said second plurality of digital circuits to the inputs of other selected ones of said second plurality of digital circuits in series to define a second test signal path comprising at least two operational signal paths connected in series so that a second test signal applied to the input of said second test signal path in the test mode propagates through said second test signal path, whereby the propagation delays through said first and second test signal paths are the sum of the individual propagation delays through each of the digital circuits in the test signal path, respectively, and are substantially longer than the propagation delay through any of said operational signal paths and can be accurately and directly measured with said test equipment without further processing.

Claim 12

A digital integrated circuit having an operation mode and a test mode comprising: a first plurality of digital circuits, each having an operational signal path therethrough from an input to an output; a second plurality of digital circuits, each having an operational signal path therethrough from an input to an output, said digital circuits each being selected from combinational logic, latching circuitry and combinations thereof; a first control means for permitting measurement of propagation delay through said first plurality of digital circuits with test equipment having an operating speed that is comparable to the operating speed of said digital circuits, said first control means comprising intercoupling gate means and means connecting the gate means between separate digital circuits, said gate means being responsive to a first test mode signal for individually coupling the outputs of selected ones of said first plurality of digital circuits to the inputs of other selected ones of said first plurality of digital circuits in series to define a first test signal path comprising at least two operational signal paths connected in series so that a first test signal applied to the input of said first test signal path in the test mode propagates through said first test signal path; a second control means for permitting measurement of propagation delay through said second plurality of digital circuits with said test equipment, said second control means comprising intercoupling means responsive to a second test mode signal for individually coupling the outputs of selected ones of said second plurality of digital circuits to the inputs of other selected ones of said second plurality of digital circuits in series to define a second test signal path comprising at least two operational signal paths connected in series so that a second test signal applied to the input of said second test signal path in the test mode propagates through said second test signal path, whereby the propagation delays through said first and second test signal paths are the sum of the individual propagation delays through each of the digital circuits in the test signal path, respectively, and are substantially longer than the propagation delay through any of said operational signal paths and can be accurately and directly measured with said test equipment without further processing.

Claim 13

A digital integrated circuit as defined in claim 9 wherein said first test mode signal is commonly connected to said first control means and to said second control means so that said first test signal path and said second test signal path are commonly controlled.

Claim 14

A digital integrated circuit as defined in claim 1 including at least one clocked circuit element, said test signal path being defined to bypass said clocked circuit element.

Claim 15

A digital integrated circuit as defined in claim 9 including at least one clocked circuit element in each of the said first and second digital circuits, said test signal path being defined to bypass said clocked circuit elements.