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US4875206A
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High bandwidth interleaved buffer memory and control
Assignee: AMERICAN TELEPHONE AND TELEGRAPH COMOPANY AT&T BELL LABORATORIES
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Filing: 1988-03-31
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Granted: 1989-10-17
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Expires: 2008-03-31
Abstract
Abstract A high capacity metropolitan area network (MAN) is described. Data traffic from users is connected to data concentrators at the edge of the network, and is transmitted over fiber optic data links to a hub where the data is switched. The hub includes a plurality of data switching modules, each having a control means, and each connected to a distributed control space division switch. Advantageously, the data switching modules, whose inputs are connected to the concentrators, perform all checking and routing functions, while the 1024x1024 maximum size space division switch, whose outputs are connected to the concentrators, provides a large fan-out distribution network for reaching many concentrators from each data switching module. Distributed control of the space division switch permits several million connection and disconnection actions to be performed each second, while the pipelined and parallel operation within the control means permits each of the 256 switching modules to process at least 50,000 transactions per second. The data switching modules chain groups of incoming packets destined for a common outlet of the space division switch so that only one connection in that switch is required for transmitting each group of chained packets from a data switching module to a concentrator. MAN provides security features including a port identification supplied by the data concentrators, and a check that each packet is from an authorized source user, transmitting on a port associated with that user, to an authorized destination user that is in the same group (virtual network) as the source user. The data switching modules each use a synchronous data ring for transporting data packets between data link handlers and a plurality of memory access controllers and their associated memory modules.
Inventors
- 👤 Robert K. Nichols
- 👤 Gary A. Roediger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:49
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; Y; Y10; Y10S; Y10S370/00; Y10S370/901; Y10S370/902; Y10S370/903; Y10S370/907
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
87 words
A method communicating between a plurality of memory modules each having a memory controller and at least one data link controller over a synchronous data ring, comprising the steps of: assigning to each combination, of a memory controller and a data link controller, at least one time slot of said synchronous data ring interconnecting said plurality of memory controllers and said at least one data link controller; and transmitting data between a memory controller and a data link controller on the time slot assigned for that combination.
Claim 2
Independent Claim
87 words
A method communicating between a plurality of memory modules each having a memory controller and at least one data link controller over a synchronous data ring, comprising the steps of: assigning to each combination, of a memory controller and a data link controller, at least one time slot of said synchronous data ring interconnecting said plurality of memory controllers and said at least one data link controller; and transmitting data between a memory controller and a data link controller on the time slot assigned for that combination.
Claim 3
Dependent Claim
37 words
The method of claim 1 further comprising the step of: initializing said memory controller with a memory address and a count of number of words to be transmitted from storage in memory starting with said memory address.
Claim 4
Dependent Claim
22 words
The method of claim 2 wherein said initializing comprises transmitting a control word from said data link controller to said memory controller.
Claim 5
Dependent Claim
50 words
The method of claim 1 wherein a single time slot is assigned for transmitting data from one of said at least one data link controllers to one of said memory controllers, and for transmitting data from said one memory controller to one of said at least one data link controllers.
Claim 6
Dependent Claim
247 words
Apparatus for communicating between a plurality of input data link controllers, a plurality of memory modules, and a plurality of output data link controllers, comprising: a synchronous data ring having one time slot assigned for each combination of an input data link controller and a memory module, said time slot also being used for communicating between said memory module and an output data link controller; and further having a plurality of time slots for sending control signals from each of said plurality of input data link controllers and said plurality of output data link controllers to said plurality of memory modules; each of said memory modules comprising a direct memory access unit for taking data from said synchronous ring for storing in a memory array of an associated memory module and for reading data from said memory array of said associated memory module to said synchronous data ring; wherein each of said plurality of input data link controllers sends a control address to all of said direct memory access units for storing data received from said each of said plurality of input data link controllers in said associated memory array at an address starting with said control address; and wherein each of said plurality of output data link controllers sends another control word to all of said direct memory access units for reading data from said memory array for delivery by said synchronous data ring to an output data link controller that sent said another control word.
Claim 7
Dependent Claim
247 words
Apparatus for communicating between a plurality of input data link controllers, a plurality of memory modules, and a plurality of output data link controllers, comprising: a synchronous data ring having one time slot assigned for each combination of an input data link controller and a memory module, said time slot also being used for communicating between said memory module and an output data link controller; and further having a plurality of time slots for sending control signals from each of said plurality of input data link controllers and said plurality of output data link controllers to said plurality of memory modules; each of said memory modules comprising a direct memory access unit for taking data from said synchronous ring for storing in a memory array of an associated memory module and for reading data from said memory array of said associated memory module to said synchronous data ring; wherein each of said plurality of input data link controllers sends a control address to all of said direct memory access units for storing data received from said each of said plurality of input data link controllers in said associated memory array at an address starting with said control address; and wherein each of said plurality of output data link controllers sends another control word to all of said direct memory access units for reading data from said memory array for delivery by said synchronous data ring to an output data link controller that sent said another control word.
Claim 8
Dependent Claim
52 words
The apparatus of claim 5 further comprising a central control means for supplying addresses to said plurality of input and said plurality of output data link controllers, wherein said central control means has access to said synchronous data ring in a time slot for accessing data in any of said memory modules.
Claim 9
Dependent Claim
106 words
Apparatus for communicating data between a plurality of memory modules and at least one data link controller, comprising: a plurality of memory access controllers, each one of said plurality of memory access controllers for controlling one of said memory modules; and a synchronous data ring interconnecting said at least one data link controller and said plurality of memory access controllers; each combination of one of said memory access controllers and one of said at least one data link controllers being assigned one time slot of a repetitive time frame for the transmission of data between said one data link controller and said one memory access controller.
Claim 10
Dependent Claim
106 words
Apparatus for communicating data between a plurality of memory modules and at least one data link controller, comprising: a plurality of memory access controllers, each one of said plurality of memory access controllers for controlling one of said memory modules; and a synchronous data ring interconnecting said at least one data link controller and said plurality of memory access controllers; each combination of one of said memory access controllers and one of said at least one data link controllers being assigned one time slot of a repetitive time frame for the transmission of data between said one data link controller and said one memory access controller.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-16 | 1993-04-17 | 1993-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-16 | 1997-04-17 | 1997-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-16 | 2001-04-17 | 2001-10-17 | $7700.00 | Window Closed / Lapsed |