US4875151A
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Two transistor full wave rectifier
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1986-08-11
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Granted: 1989-10-17
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Expires: 2006-08-11
Abstract
Abstract An integrated circuit two transistor full wave rectifier suitable for fabrication in a CMOS, NMOS or PMOS process and characterized by a high level of integration based upon shared utilization of doped regions. In one form, the full wave rectifier is configured from two diode connected field effect transistors and two parasitic p-n junctions, all formed in a substrate region of common impurity type.
Inventors
- 👤 Daniel L. Ellsworth
- 👤 Maurice M. Moll
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:29
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H02; H02M; H02M7/00; H02M7/02; H02M7/04; H02M7/12; H02M7/21; H02M7/217; H10D84/85
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
179 words
A two transistor full wave rectifier, comprising: first and second field effect transistors of first conductivity type, each resident in a substrate region of second conductivity type and each having respective first and second electrode regions and a gate electrode; a first node, defining a common connection of a DC load terminal, the first electrode region of the first field effect transistor and the first electrode region of the second field effect transistor; a second node, defining a common connection of the second electrode region of the first field effect transistor, the gate electrode of the first field effect transistor and the first of two connections to a source of AC voltage; a third node, defining a common connection of the second electrode region of the second field effect transistor, the gate electrode of the second field effect transistor and the second of the two connections to the source of AC voltage; and a fourth node, defining a common connection of the other DC load terminal and the second conductivity type substrate region of each resident field effect transistor.
Claim 2
Dependent Claim
179 words
A two transistor full wave rectifier, comprising: first and second field effect transistors of first conductivity type, each resident in a substrate region of second conductivity type and each having respective first and second electrode regions and a gate electrode; a first node, defining a common connection of a DC load terminal, the first electrode region of the first field effect transistor and the first electrode region of the second field effect transistor; a second node, defining a common connection of the second electrode region of the first field effect transistor, the gate electrode of the first field effect transistor and the first of two connections to a source of AC voltage; a third node, defining a common connection of the second electrode region of the second field effect transistor, the gate electrode of the second field effect transistor and the second of the two connections to the source of AC voltage; and a fourth node, defining a common connection of the other DC load terminal and the second conductivity type substrate region of each resident field effect transistor.
Claim 3
Dependent Claim
39 words
The apparatus as recited in claim 1, wherein the first electrode region of the first field effect transistor and the first electrode region of the second field effect transistor are defined by a single region of first conductivity type.
Claim 4
Dependent Claim
18 words
The apparatus recited in claim 2, wherein the first and second field effect transistors are enhancement type devices.
Claim 5
Dependent Claim
29 words
The apparatus recited in claim 3, wherein the second conductivity type substrate region of each resident field effect transistor is a single ohmically continuous region of second conductivity type.
Claim 6
Dependent Claim
21 words
The apparatus recited in claim 4, wherein the single ohmically continuous region includes multiple heavily doped contact regions for carrier trapping.
Claim 7
Dependent Claim
31 words
The apparatus recited in claim 2, further including in a separate well of first conductivity type a region of second conductivity type connected to the load and providing capacitive filtering therein.
Claim 8
Dependent Claim
141 words
A two transistor full wave rectifier, comprising: first and second p-channel field effect transistors each having a gate electrode and source and drain regions fabricated in an n-type substrate; a first node, defining a common connection of a DC load terminal and a source region of each p-channel field effect transistor with ground potential; a second node, defining a common connection of the gate electrode and the drain region of the first p-channel field effect transistor with the first of two connections to a source of AC voltage; a third node, defining a common connection of the gate electrode and the drain region of the second p-channel field effect transistor with the second of the two connections to the source of AC voltage; and a fourth node, defining a common connection of the other DC load terminal to the n-type substrate.
Claim 9
Dependent Claim
141 words
A two transistor full wave rectifier, comprising: first and second p-channel field effect transistors each having a gate electrode and source and drain regions fabricated in an n-type substrate; a first node, defining a common connection of a DC load terminal and a source region of each p-channel field effect transistor with ground potential; a second node, defining a common connection of the gate electrode and the drain region of the first p-channel field effect transistor with the first of two connections to a source of AC voltage; a third node, defining a common connection of the gate electrode and the drain region of the second p-channel field effect transistor with the second of the two connections to the source of AC voltage; and a fourth node, defining a common connection of the other DC load terminal to the n-type substrate.
Claim 10
Dependent Claim
22 words
The apparatus recited in claim 7, wherein the first and second p-channel field effect transistors are enhancement type devices when back biased.
Claim 11
Dependent Claim
24 words
The apparatus recited in claim 8, wherein the source regions of the first node are comprised of a single p-type region in the substrate.
Claim 12
Dependent Claim
141 words
A two transistor full wave rectifier, comprising: first and second n-channel field effect transistors each having a gate electrode and source and drain regions fabricated in a p-type substrate; a first node, defining a common connection of a DC load terminal with a source region of each n-channel field effect transistor; a second node, defining a common connection of the gate electrode and the drain region of the first n-channel field effect transistor with the first of two connections to the source of AC voltage; a third node, defining a common connection of the gate electrode and the drain region of the second n-channel field effect transistor with the second of the two connections to the source of AC voltage; and a fourth node, defining a common connection of the other DC load terminal and the n-type substrate with ground potential.
Claim 13
Dependent Claim
141 words
A two transistor full wave rectifier, comprising: first and second n-channel field effect transistors each having a gate electrode and source and drain regions fabricated in a p-type substrate; a first node, defining a common connection of a DC load terminal with a source region of each n-channel field effect transistor; a second node, defining a common connection of the gate electrode and the drain region of the first n-channel field effect transistor with the first of two connections to the source of AC voltage; a third node, defining a common connection of the gate electrode and the drain region of the second n-channel field effect transistor with the second of the two connections to the source of AC voltage; and a fourth node, defining a common connection of the other DC load terminal and the n-type substrate with ground potential.
Claim 14
Dependent Claim
19 words
The apparatus recited in claim 10, wherein the first and second n-channel field effect transistors are enhancement type devices.
Claim 15
Dependent Claim
24 words
The apparatus recited in claim 11, wherein the source regions of the first node are comprised of a single n-type region in the substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-16 | 1993-04-17 | 1993-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-16 | 1997-04-17 | 1997-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-16 | 2001-04-17 | 2001-10-17 | $7700.00 | Window Closed / Lapsed |