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US4873668A
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Integrated circuit in complementary circuit technology comprising a substrate bias generator
Assignee: Siemens AG
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Filing: 1987-08-17
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Granted: 1989-10-10
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Expires: 2007-08-17
Abstract
Abstract An integrated circuit executed in complementary circuit technology, has a substrate bias generator (16) which connects the substrate (1) to a substrate bias. A well (2) of opposite conductivity is inserted into the substrate (1), and FETs with complementary channels are inserted into the substrate (1) and into the well (2), respectively. The source regions (3) of the FET's of first conductivity lie at ground potential. In order to avoid latch-up effects, the output (17) of the substrate bias generator (16) is connected via an electronic switch (S1) to a circuit point (8) lying at ground potential, the switch being driven via a time-delay circuit (24) charged with the supply voltage so that it opens with a prescribed time-delay after the supply voltage is applied.
Inventors
- 👤 Josef Winnerl
- 👤 Dezso Takacs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:25
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; H; H10; H10D; H10D89/00; H10D89/211; H10D89/213; H10D89/215; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
225 words
In an integrated circuit executed in complementary circuit technology comprising a pair of field effect transistors (T1, T2) of different channel types, said first field effect transistor (T1) being provided in a doped semiconductor substrate (1) of a first conductivity type and at least one second field effect transistor (T2) being arranged in a well-shaped semiconductor zone (2) of a second conductivity type provided in said semiconductor substrate (1), said semiconductor zone adapted to be wired to a supply voltage (V DD ), whereby a terminal region (3) of at least one first field effect transistor (T1) is charged with a grounded potential (VSS), the semiconductor substrate adapted to be connected to the output (17) of a substrate bias generator (16) to which the grounded potential and the supply voltage are supplied and which biases the p-n junction between the terminal region (3) of the first field effect transistor lying at ground potential and the semiconductor substrate (1) in non-conducting direction, the combination comprising; an electronic switch for connecting the output (17) of the substrate bias generator (16) to ground potential for a predetermined time after said supply voltage (V DD ) is applied; and a time delay circuit connected between said electronic switch and said supply voltage (V DD ) for opening said switch in response to said supply voltage after said predetermined time.
Claim 2
Dependent Claim
225 words
In an integrated circuit executed in complementary circuit technology comprising a pair of field effect transistors (T1, T2) of different channel types, said first field effect transistor (T1) being provided in a doped semiconductor substrate (1) of a first conductivity type and at least one second field effect transistor (T2) being arranged in a well-shaped semiconductor zone (2) of a second conductivity type provided in said semiconductor substrate (1), said semiconductor zone adapted to be wired to a supply voltage (V DD ), whereby a terminal region (3) of at least one first field effect transistor (T1) is charged with a grounded potential (VSS), the semiconductor substrate adapted to be connected to the output (17) of a substrate bias generator (16) to which the grounded potential and the supply voltage are supplied and which biases the p-n junction between the terminal region (3) of the first field effect transistor lying at ground potential and the semiconductor substrate (1) in non-conducting direction, the combination comprising; an electronic switch for connecting the output (17) of the substrate bias generator (16) to ground potential for a predetermined time after said supply voltage (V DD ) is applied; and a time delay circuit connected between said electronic switch and said supply voltage (V DD ) for opening said switch in response to said supply voltage after said predetermined time.
Claim 3
Dependent Claim
26 words
The integrated circuit according to claim 1, wherein said substrate bias generator (16) is integrated with said field effect transistor on the same semiconductor substrate (1).
Claim 4
Dependent Claim
119 words
The integrated circuit according to claim 1 or 2, including means for connecting the output (17) of said substrate bias generator (16) to a first semiconductor region (20) of the second conductivity type inserted into the semiconductor substrate; a second semiconductor region (21) of the second conductivity type inserted into the semiconductor substrate and connected to ground potentiaI; and a region of the semiconductor substrate (1) lying between these two semiconductor regions (20, 21) being covered by a gate (22) separated from the boundary surface (1a) of the semiconductor substrate by a thin, electrically insulating layer (23), whereby said gate, together with the two semiconductor regions, forms a first field effect switching transistor which constitutes said electronic switch (S1).
Claim 5
Dependent Claim
49 words
The integrated circuit according to claim 1 or 2, wherein said time-delay circuit (24) is composed of a RC element and including means for connecting said RC element first, to a terminal (14) charged with the supply voltage (V DD ) and, second, to ground potential (V SS ).
Claim 6
Dependent Claim
81 words
The integrated circuit according to claim 4, wherein said RC element comprises a load element (27) and a capacitor (T3), said load element being composed of a third field effect transistor whose gate is connected to its drain terminal, and said capacitor (T3) being composed of a fourth field effect transistor whose source and drain terminals are connected to on another to form a first capacitor terminal, said gate terminal of said forth field effect transistor constituting the second capacitor terminal.
Claim 7
Dependent Claim
88 words
The integrated circuit according to claim 1 or 2, wherein the output (25) of the time-delay circuit (24) is connected to an inverting amplifier (26) which contains a series circuit of a fifth and a sixth field effect transistor (T4, T5) of different channel types and whose gates are connected to the output (25) of the time-delay circuit (24); and said series circuit is connected, first, to the supply voltage VDD) via a further load element and, second, to the output (17) of the substrate bias generator (16).
Claim 8
Dependent Claim
30 words
The integrated circuit according to claim 1 or 2, including a dynamic semiconductor memory having high integration density, said integrated circuit being connected to said memory as an input/output circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-09 | 1993-04-10 | 1993-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-09 | 1997-04-10 | 1997-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-09 | 2001-04-10 | 2001-10-10 | $7700.00 | Window Closed / Lapsed |