US4873460A
Expired / Lapsed
US
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Monolithic transistor gate energy recovery system
Assignee: California Institute of Technology
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Filing: 1988-11-16
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Granted: 1989-10-10
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Expires: 2008-11-16
Abstract
Abstract Energy is recovered from an insulated gate semiconductor switch, such as a MOSFET, that is otherwise lost in the gate capacitance by producing a notch in the gate control voltage for an interval B following an interval A after initial application of a gate control voltage pulse for turning the switch on, and a notch for an interval C following termination of the gate control voltage pulse followed by interval D during which the switch is turned on again, where each interval is a period ΔT given by ##EQU1## L s is the inductance (discrete and/or parasitic) in series with the gate electrode of the insulated gate semiconductor switch, and C in is the capacitance of that switch between its gate and source electrodes. The interval ΔT may be provided directly by timing in a pulse forming circuit for the gate control voltage applied, or adaptively by sensing the gate voltage v g and comparing it with fixed progressively higher voltages v 1 , v 2 and v 3 , where v 2 is intermediate v 1 and v 3 which correspond to the lower and upper levels of v g as the switch is turned off and on.
Inventors
- 👤 Wally E. Rippel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:34
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/04; H03K17/041; H03K17/0412; H03K17/04123; H03K17/51; H03K17/56; H03K17/687
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
243 words
A pulse forming circuit for control of the gate of an insulated gate semiconductor switch having capacitance between its source and gate electrodes, and inductance in series with its gate electrode comprising means for producing a notch in an applied input control voltage after an interval A following the initial application of the input control voltage for an interval B, and a notch for an interval C following termination of the applied input control voltage followed by a pulse of an interval D, where each interval is a period ΔT given by ##EQU3## where L s is said series conductance and C in is said capacitance, comprising means responsive to the initial application of said control input voltage for determining said intervals A and B and means responsive to the termination of said control input voltage for determining said intervals C and D, means responsive to said intervals A and B for producing a notch after initial application of said control input voltage, and means responsive to said intervals C and D for producing a notch after termination of said control input voltage, whereby said notches at the leading and trailing ends of said control input voltage to the gate of said transistor will switch said gate to an off level during said notches of said intervals B and C while switching said gate to an on level during intervals A and D and for the entire period between intervals B and C.
Claim 2
Dependent Claim
243 words
A pulse forming circuit for control of the gate of an insulated gate semiconductor switch having capacitance between its source and gate electrodes, and inductance in series with its gate electrode comprising means for producing a notch in an applied input control voltage after an interval A following the initial application of the input control voltage for an interval B, and a notch for an interval C following termination of the applied input control voltage followed by a pulse of an interval D, where each interval is a period ΔT given by ##EQU3## where L s is said series conductance and C in is said capacitance, comprising means responsive to the initial application of said control input voltage for determining said intervals A and B and means responsive to the termination of said control input voltage for determining said intervals C and D, means responsive to said intervals A and B for producing a notch after initial application of said control input voltage, and means responsive to said intervals C and D for producing a notch after termination of said control input voltage, whereby said notches at the leading and trailing ends of said control input voltage to the gate of said transistor will switch said gate to an off level during said notches of said intervals B and C while switching said gate to an on level during intervals A and D and for the entire period between intervals B and C.
Claim 3
Dependent Claim
25 words
Apparatus as defined in claim 1 wherein said intervals, A, B, C and D are timed by timing circuits, each interval being equal to ##EQU4##
Claim 4
Dependent Claim
143 words
Apparatus as defined in claim 1 wherein said intervals A, B, C and D are determined by sensing the gate voltage v g of said transistor and switching from interval A to interval B when said gate voltage v g reaches an intermediate threshold voltage v 2 between off and on, terminating said interval B upon sensing said gate voltage is no longer below a higher threshold voltage v 3 , switching to interval C upon sensing that the control input voltage has terminated, switching to interval D upon sensing that said gate voltage has dropped below said threshold voltage v 2 , and terminating said interval D upon sensing that said gate voltage is no longer greater than a threshold voltage v 1 , where said threshold voltages v 1 , v 2 and v 3 are progressively higher constant voltage levels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-09 | 1993-04-10 | 1993-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-09 | 1997-04-10 | 1997-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-09 | 2001-04-10 | 2001-10-10 | $7700.00 | Window Closed / Lapsed |