Digital decimation filter

Claim 1

A digital filter circuit for implementing a decimation filter with the transfer function: H(z)=b(1-z.sup.-kn)(1-z.sup.-n).sup.m-1 /(1-z.sup.-1).sup.m, where z is the complex frequency variable, k is an integral parameter for adjusting the bandwidth of the digital filter circuit, m is a number which specifies how many filter sections are cascaded, n is the integral quotient of the input sampling frequency of the input data and the output sampling frequency of the output data, and b is the nearest power of two ("2 -q ") less than or equal to 1/kn m , with terms of the form (1-z -n ) and (1-z -kn ) representing differentiators, and terms of the form (1-z -1 ) representing integrators, the digital filter circuit comprising a cascade arrangement of the following sections: a multiplier that receives an input signal to be filtered and that multiples the input signal by the factor 2 -q ; m-1 integrators, each of the integrators having an input and an output and comprising: an adder having first and second inputs and a sum output, the adder in each integrator having its first input and its sum output interposed between the input and the output of the integrator; and a delay element having an input and an output, the input of the delay element connected to the output of the adder in the integrator and the output of the delay element connected to the second input of the adder, the delay element introducing a delay equal to the period of the input sampling frequency; an mth integrator having an input and an output, the mth integrator comprising: an adder having first and second inputs and a sum output, the adder having its first input and its sum output interposed between the input and the output of the integrator; and a delay element having an input and an output, the input of the delay element connected to the output of the adder and the output of the delay element connected to the second input of the adder, the delay element introducing a delay equal to the period of the input sampling frequency, the delay element being reset by the output sampling clock to thereby reset the sum; a sampling device switched at the pulse repetition rate of the output sampling clock; m-2 differentiators each containing a delay element which introduces a delay equal to the period of the output sampling clock; and an (m-1)st differentiator containing k delay elements which each introduce a delay equal to the period of the output sampling clock.